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參數(shù)資料
| 型號： | DS75U+T&R |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 11/14頁 |
| 文件大小： | 183K |
| 描述： | IC THERMOMETER/STAT DIG 8-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 功能： | 溫度計，恒溫計 |
| 傳感器類型： | 內(nèi)部 |
| 感應(yīng)溫度： | -55°C ~ 125°C |
| 精確度： | ±3°C（最小值） |
| 拓撲： | ADC（三角積分型），比較器，寄存器庫 |
| 輸出類型： | I²C?/SMBus? |
| 輸出警報： | 無 |
| 輸出風(fēng)扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS75
11 of 14
START Condition: Signal generated by the master to indicate the beginning of a data transfer on the
bus. The master generates a START condition by pulling SDA from high to low while SCL is high (see
Figure 6). A repeated START is sometimes used at the end of a data transfer (instead of a STOP) to
indicate that the master will perform another operation.
STOP Condition: Signal generated by the master to indicate the end of a data transfer on the bus. The
master generates a STOP condition by transitioning SDA from low to high while SCL is high (see Figure
6). After the STOP is issued, the master releases the bus to its idle state.
Acknowledge (ACK): When a device (either master or slave) is acting as a receiver, it must generate an
acknowledge (ACK) on the SDA line after receiving every byte of data. The receiving device performs an
ACK by pulling the SDA line low for an entire SCL period (see Figure 6). During the ACK clock cycle,
the transmitting device must release SDA. A variation on the ACK signal is the not acknowledge
(NACK). When the master device is acting as a receiver, it uses a NACK instead of an ACK after the last
data byte to indicate that it is finished receiving data. The master indicates a NACK by leaving the SDA
line high during the ACK clock cycle.
Slave Address: Every slave device on the bus has a unique 7-bit address that allows the master to access
that device. The DS75s 7-bit bus address is 1 0 0 1 A
2
A
1
A
0
, where A
2
, A
1
and A
0
are user-selectable via
the corresponding input pins. The three address pins allow up to eight DS75s to be multi-dropped on the
same bus.
Address Byte: The control byte is transmitted by the master and consists of the 7-bit slave address plus a
read/write (R/W?/SPAN>?/SPAN>) bit (see Figure 7). If the master is going to read data from the slave device then R/W?/SPAN>?/SPAN> =
1, and if the master is going to write data to the slave device then R/W?/SPAN>?/SPAN> = 0.
Pointer Byte: The pointer byte is used by the master to tell the DS75 which register is going to be
accessed during communication. The six LSbs of the pointer byte (see Figure 8) are always 0 and the two
LSbs correspond to the desired register as shown in Table 7.
Figure 6. START, STOP, AND ACK SIGNALS
Figure 7. ADDRESS BYTE
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1
0
0
1
A
2
A
1
A
0
R/W?/SPAN>?/SPAN>
Figure 8. POINTER BYTE
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SCL
SDA
START
Condition
STOP
Condition
ACK (or NACK)
From Receiver
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