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參數資料
| 型號： | HIP1020CK-T |
| 廠商： | Intersil |
| 文件頁數： | 5/6頁 |
| 文件大?。?/td> | 331K |
| 描述： | IC CTRLR HOT PLUG SOT23-5 |
| 標準包裝： | 3,000 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 5V，12V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應商設備封裝： | SOT-23-5 |
| 包裝： | 帶卷 (TR) |
5
The MOSFETs in Table 1 were selected based on the
assumption that at most 2% the of the 5V or 3.3V-bus
voltage could appear across the 5V or 3.3V MOSFET, and
that at most 4% of the 12V-bus voltage could appear across
the 12V MOSFET. The worst-case voltage drop occurs
during a 100祍 current transient given in the Maximum-
Peak-Current column. Longer transients may not be
tolerable by the MOSFET depending on its junction
temperature prior to the transient.
In most cases, the given Mounting-Pad Area is required to
achieve the Maximum-Average-Current rating. It assumes 1-
oz. copper, zero air flow, and an ambient temperature not
exceeding 50
o
C. The Mounting-Pad Area is the approximate
area of a rectangle encompassing the MOSFET package
and its leads. The r
DS(ON)
numbers assume the device has
reached thermal equillibrium at the Maximum-Average-
Current. In some cases, the thermal capabilities as well as
r
DS(ON)
can be improved by using larger pads, heavier
copper, air flow, or lower ambient temperature.
Protection from Unwanted Turn On
A dv/dt-activated clamp circuit is internally connected to
LGATE (pin 4), and is active when the chip is not powered. It
is activated when the voltage on either LGATE or HGATE
rises too quickly, and it immediately provides a low-
impedance ground path for current from either gate pin.
The purpose of the dv/dt-activated clamp circuit is to prevent
unwanted turn on of the power MOSFETs during a hot
insertion event. When a Device-Bay peripheral is inserted
into the bay, the power pins on the peripheral are brought
into contact with the already-energized mating contacts in
the bay. This results in a very fast-rising voltage edge on the
drains of the power MOSFETs which can inject current
through the gate-to-drain capacitance and briefly turn on the
power MOSFET. The result is a momentary dip in the rail
voltage which can effect the devices operation as well as the
operation of any other device already connected and
potentially the host system itself. Without the dv/dt-activated
clamp, a decoupling capacitor would be needed between
each power MOSFET drain and ground using up valuable
board space and adding unnecessary cost. The HIP1020
solves this problem by providing a path for capacitively-
coupled current to reach ground.
Increasing the Rise Time
The HIP1020 has an internal-ramping charge pump that
increases the voltage to the power MOSFETs in a
predictable controlled manner allowing soft turn on of most
types of loads. It is possible that some types of load would
require slower turn on. This could arise when a load has a
large capacitive component or for some other reason
requires an extraordinarily high starting current. Without the
external capacitor, C1 (see Figure 1), the ramp rate is about
5V/ms. A capacitor between HGATE and ground will slow the
rise time of both gate voltages to a rate given by
In Equation 1, C1 is the value of capacitor in Farads required
to achieve a rise rate of dv/dt in V/s, and I
HGATE
is current
output of pin 4 given in Amperes as shown in the Electrical
Specifications section of this data sheet. Figures 2 through
5 show gate voltage waveforms for selected values of C1.
TABLE 1. DEVICE-BAY MOSFET SELECTION GUIDE FOR PERIPHERAL-POWER CONTROL
INTERSIL
PART NO.
MOUNTING-PAD
AREA (IN
2
)
PACKAGE
r
DS(ON)
(m&)
BUS
(VOLTAGE)
MAXIMUM
AVERAGE CURRENT
MAXIMUM
PEAK CURRENT
HUF76105DK8
0.05
SO-8
Dual
63
12
d3A (Note 4)
d7A (Note 5)
51
5
d1A
d2A
48
3.3
d1A
d1.25A
HUF76113DK8
0.05
SO-8
Dual
43
12
d3A (Note 4)
d11A (Note 5)
or
40
5
d2A
d2.5A
HUF76113T3ST
0.08
SOT223
Single
37
3.3
d1.5A
d1.5A
HUF76131SK8
0.05
SO-8
Single
17
12
d6A (Note 4)
d25A (Note 5)
16
5
d5A (Note 4)
d6A (Note 5)
15
3.3
d4A
d4A
HUF76143S3S
0.31
TO-263
Single
7
3.3
d9A (Note 4)
d9A (Note 5)
NOTES:
4. Maximum-Average-Current level meets or exceeds the Device-Bay specified level for a 30s peak .
5. Maximum-Peak-Current level meets or exceeds the Device-Bay specified level for a 100祍 transient .
C1
I
HGATE
dv
dt
----- -
?nbsp ?/DIV>
?nbsp ?/DIV>
-------------------- -
=
(EQ. 1)
HIP1020
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| HIP1020CKZ-T | 功能描述:熱插拔功率分布 DEVICE BAY PWR CNTRLR RoHS:否 制造商:Texas Instruments 產品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| HIP1030 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1A High Side Driver with Overload Protection |
| HIP1030_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1A High Side Driver with Overload Protection |
| HIP1030AS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:1A High Side Driver with Overload Protection |
| HIP1031 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Half Amp High Side Driver with Overload Protection |
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