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參數資料
| 型號： | ISL6173DRZA-T |
| 廠商： | Intersil |
| 文件頁數： | 5/20頁 |
| 文件大小： | 453K |
| 描述： | IC CTRLR HOT SWAP DUAL LV 28-QFN |
| 標準包裝： | 6,000 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | 2.25 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
5
FN9186.3
January 3, 2006
Absolute Maximum Ratings
Thermal Information
VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +12V
ENx
, RTR
/LTCH, SNSx, PGx
, FLTx, VSx, CTx, UVx,
SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC
Output Current . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . .1750V
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .125V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1750V
Operating Conditions
VBIAS/VIN1 Supply Voltage Range. . . . . . . . . . . .+2.25V to +3.63V
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . . . 0癈 to 85癈
Thermal Resistance (Typical, Notes 1, 4) ?/DIV>
JA
(癈/W) ?/DIV>
JC
(癈/W)
5x5 QFN Package . . . . . . . . . . . . . . . .
42
12.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150癈
Maximum Storage Temperature Range. . . . . . . . . . .-65癈 to 150癈
For recommended soldering conditions, see Tech Brief TB389.
(QFN - Leads Only)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. ?/DIV>
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See
Tech Brief TB379.
2. All voltages are relative to GND, unless otherwise specified.
3. 1V (min) on the BIAS pin required for FLT
to be valid.
4. For ?/DIV>
JC
, the case temp location is the center of the exposed metal pad on the package underside.
Electrical Specifications V
DD
= 2.5V to +3.3V, V
S
= 1V ,T
A
= T
J
= 0癈 - 85癈, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT REGULATION CONTROL
ISET Current
I
SET_ft
R
OCREF
= 14.7k&
18.7
20
21.3
礎
Partial Temp Range I
SET
Current
I
SET_pt
R
OCREF
= 14.7k&
T
J
= 25
o
C to 60
o
C
19
20
21
礎
Current Limit Amp Offset Voltage
Vio_ft
V
VS
- V
SNS
with I
OUT
= 0A
-2
2
mV
Partial Temp. Current Limit Amp Offset
Voltage
Vio_pt
V
VS
- V
SNS
with I
OUT
= 0A
T
J
= 25癈 to 60癈
-1
1
mV
Current Regulation Threshold Voltage
V
CRVTH_1
RISET = 1.25K, I
SET
= 20礎
23
25
27
mV
Current Regulation Accuracy
V
CRVTH_1
R
RISET = 1.25K, I
SET
= 20礎
-8
+8
%
Current Regulation Threshold Voltage
V
CRVTH_2
RISET = 2.50K, I
SET
= 20礎
48
50
52
mV
Current Regulation Accuracy
V
CRVTH_2
R
RISET = 2.50K, I
SET
= 20礎
-4
+4
%
Current Regulation Threshold Voltage
V
CRVTH_3
RISET = 0.499K, I
SET
= 20礎
8
10
12
mV
Current Regulation Accuracy
V
CRVTH_3
R
RISET = 0.499K, I
SET
= 20礎
-20
+20
%
CT Threshold Voltage
V
CT_Vth
1.128
1.178
1.202
V
CT Charging Current
I
CT
10
礎
GATE DRIVE
GATE Response Time from WOC (Open)
pd_woc_open
GATE open
100mV of overdrive on the WOC
comparator
3
ns
GATE Response Time from WOC
(Loaded)
pd_woc_load
GATE = 1nF
100
ns
GATE Response Time in Current
Regulation mode (Loaded)
pd_cr_load
GATE = 1nF
120% Load Current
5
祍
GATE Turn-On Current
IGATE
GATE = 2V, V
VS
= 2V, V
SNS
= 2.1V
21
24
27
礎
ISL6173
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