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參數資料
| 型號： | MC10EPT20DTR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3.3VLVTTL/LVCMOS to Differential LVPECL Translator |
| 中文描述： | TTL/CMOS TO PECL TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO8 |
| 封裝： | PLASTIC, TSSOP-8 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 64K |
| 代理商： | MC10EPT20DTR2 |
Semiconductor Components Industries, LLC, 1999
September, 1999 – Rev. 1.0
1
Publication Order Number:
MC10EPT20/D
The MC10EPT20 is a LVTTL/LVCMOS to differential LVPECL
translator. Because LVPECL (Positive ECL) levels are used only
+3.3V and ground are required. The small outline 8–lead SOIC
package and the single gate of the EPT20 makes it ideal for those
applications where space, performance, and low power are at a
premium.
390ps Typical Propagation Delay
High Bandwidth to 1.0 GHz Typical
Differential LVPECL Outputs
Small Outline SOIC Package
PNP LVTTL Inputs for Minimal Loading
VCC Range of 3.0V to 3.6V
ESD Protection: >1.5KV HBM, >200V MM
Q Output will default HIGH with inputs open
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 150 devices
1
2
3
4
5
6
7
8
D
GND
VCC
Figure 1. 8–Lead Pinout
(Top View)
and Logic Diagram
Q
NC
Q
NC
NC
LVTTL
LVPECL
SO–8
D SUFFIX
CASE 751
PIN DESCRIPTION
PIN
Q, Q
D
LVTTL Input
FUNCTION
Differential LVPECL Outputs
http://onsemi.com
VCC
GND
Ground
Positive Supply
MARKING DIAGRAM
HPT20
Device
Package
Shipping
ORDERING INFORMATION
MC10EPT20D
SOIC
98 Units/Rail
MC10EPT20DR2
SOIC
2500 Tape & Reel
ALYW
1
8
1
8
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
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| MC10EPT20DTR2G | 功能描述:轉換 - 電壓電平 3.3V TTL/CMOS to Diff PECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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