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參數(shù)資料
| 型號： | MC1GH128DACA-2SA00 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | SAMSUNG MultiMediaCard |
| 中文描述： | 三星多媒體 |
| 文件頁數(shù)： | 75/102頁 |
| 文件大小： | 1384K |
| 代理商： | MC1GH128DACA-2SA00 |
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MultiMediaCard
TM
75
Sep.22.2005
Revision 0.3
6.14 Data Write
Single Block Write
The host selects the card for data write operation by CMD7.
The host sets the valid block length for block oriented data transfer (a stream write mode is also available) by CMD16.
The basic bus timing for a write operation is given in Figure 6-15. The sequence starts with a single block write command
(CMD24) which determines (in the argument field) the start address. It is responded by the card on the CMD line as usual.
The data transfer from the host starts N
WR
clock cycles after the card response was received.
The data is suffixed with CRC check bits to allow the card to check it for transmission errors. The card sends back the
CRC check result as a CRC status token on DAT0. In the case of transmission error, occurring on any of the active data
lines, the card sends a negative CRC status (‘101’) on DAT0. In the case of successful transmission, over all active data
lines, the card sends a positive CRC status (‘010’) on DAT0 and starts the data programming procedure
Figure 6-15 : Block Write Command Timing
If the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line DAT0 to
LOW. The card stops pulling down DAT0 as soon as at least one receive buffer for the defined data transfer block length
becomes free. This signalling does not give any information about the data write status which must be polled by the host.
Multiple Block Write
In multiple block write mode, the card expects continuous flow of data blocks following the initial host write command. The
data flow is terminated by a stop transmission command (CMD12). Figure 6-16 describes the timing of the data blocks
with and without card busy signal.
Host cmnd
→ ←
N
CR
cycles
→←
Card response
→
CMD
E Z Z P * P S T
Content
CRC E Z Z P
* * * * * * * * * * * *
P P P P P P P P P P
←
CRC status
→
←
Busy
→
CRC E Z Z S Status E S
CRC E Z Z X
* * * * * * * * * * * *
←
N
WR
→←
Write data
→
Z Z P * P S
content
Z Z P * P S
content
DAT0
DAT1-7
Z Z
Z Z
* * * * * *
* * * * * *
Z Z Z
Z Z Z
* * * * *
* * * * *
L * L
E Z
X Z
Card Rsp
→
CMD
E Z Z P
←
N
WR
→ ←
Write data
→
Z Z P * P S Data
+ CRC
E Z Z S Status E Z P * P S Data
+ CRC
E Z Z S Status E S L * L E Z P * P
Z Z P * P S Data
+ CRC
E Z Z X * * * X Z P * P S Data
+ CRC
E Z Z X * * * * * * * * * * X Z P * P
* * * * * * * * * * * * * * * *
P P P P P
* * * * * * * * * * * * * * * *
P
P P P P P P P P
←
CRC status
→
←
Busy
→ ←
N
WR
→
←
CRC status
→
←
N
WR
→ ←
Write data
→
DAT0
DAT1-7
Figure 6-16 : Multiple Block Write Timing
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