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參數資料
| 型號： | MC26LS30DR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual Differential Quad Single-Ended (EIA-423-A) Line Drivers |
| 中文描述： | QUAD LINE DRIVER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數： | 9/16頁 |
| 文件大小： | 108K |
| 代理商： | MC26LS30DR2 |
MC26LS30
http://onsemi.com
9
APPLICATIONS INFORMATION
(Pin numbers refer to SO–16 package only.)
Description
The MC26LS30 is a dual function line driver – it can be
configured as two differential output drivers which comply
with EIA–422–A Standard, or as four single–ended drivers
which comply with EIA–423–A Standard. The mode of
operation is selected with the Mode pin (Pin 4) and
appropriate power supplies (see Table 1). Each of the four
outputs is capable of sourcing and sinking 60 to 70 mA while
providing sufficient voltage to ensure proper data
transmission.
As differential drivers, data rates to 10 Mbaud can be
transmitted over a twisted pair for a distance determined by
the cable characteristics. EIA–422–A Standard provides
guidelines for cable length versus data rate. The advantage
of a differential (balanced) system over a single–ended
system is greater noise immunity, common mode rejection,
and higher data rates.
Where extraneous noise sources are not a problem, the
MC26LS30 may be configured as four single–ended drivers
transmitting data rates to 100 Kbaud. Crosstalk among wires
within a cable is controlled by the use of the slew rate control
pins on the MC26LS30.
Mode Selection (Differential Mode)
In this mode (Pins 4 and 8 at ground), only a +5.0 V supply
±
5% is required at V
CC
. Pins 2 and 7 are the driver inputs,
while Pins 10, 11, 14 and 15 are the outputs (see Block
Diagram on page 1). The two outputs of a driver are always
complementary and the differential voltage available at each
pair of outputs is shown in Figure 6 for V
CC
= 5.0 V. The
differential output voltage will vary directly with V
CC
. A
“high” output can only source current, while a “low” output
can only sink current (except for short circuit current – see
Figure 8).
The two outputs will be in a high impedance mode when
the respective Enable input (Pin 3 or 6) is high, or if V
CC
1.1 V. Output leakage current over a common mode range of
±
10 V is typically less than 1.0
μ
A.
The outputs have short circuit current limiting, typically,
less than 100 mA over a voltage range of 0 to +6.0 V (see
Figure 8). Short circuits should not be allowed to last
indefinitely as the IC may be damaged.
Pins 9, 12, 13 and 16 are not normally used when in this
mode, and should be left open.
(Single–Ended Mode)
In this mode (Pin 4
≥
2.0 V) V
CC
requires +5.0 V, and V
EE
requires –5.0 V, both
±
5.0%. Pins 2, 3, 6, and 7 are inputs for
the four drivers, and Pins 15, 14, 11, and 10 (respectively)
are the outputs. The four drivers are independent of each
other, and each output will be at a positive or a negative
voltage depending on its input state, the load current, and the
supply voltage. Figures 10 & 11 indicate the high and low
output voltages for V
CC
= 5.0 V, and V
EE
= –5.0 V. The graph
of Figure 10 will vary directly with V
CC
, and the graph of
Figure 11 will vary directly with V
EE
. A “high” output can
only source current, while a “low” output can only sink
current (except short circuit current – see Figure 14).
The outputs will be in a high impedance mode only if
V
CC
1.1 V. Changing V
EE
to 0 V does not set the outputs
to a high impedance mode. Leakage current over a common
mode range of
±
10 V is typically less than 1.0
μ
A.
The outputs have short circuit current limiting, typically
less than 100 mA over a voltage range of
±
6.0 V (see Figure
14). Short circuits should not be allowed to last indefinitely
as the IC may be damaged.
Capacitors connected between Pins 9, 12, 13, and 16 and
their respective outputs will provide slew rate limiting of the
output transition. Figure 16 indicates the required capacitor
value to obtain a desired rise or fall time (measured between
the 10% and 90% points). The positive and negative
transition times will be within
≈
±
5% of each other. Each
output may be set to a different slew rate if desired.
Inputs
The five inputs determine the state of the outputs in
accordance with Table 1. All inputs (regardless of the
operating mode) have a nominal threshold of +1.3 V, and
their voltage must be kept within a range of 0 V to +15 V for
proper operation. If an input is taken more than 0.3 V below
ground, excessive currents will flow, and the proper
operation of the drivers will be affected. An open pin is
equivalent to a logic high, but good design practices dictate
that inputs should never be left open. Unused inputs should
be connected to ground. The characteristics of the inputs are
shown in Figure 9.
Power Supplies
V
CC
requires +5.0 V,
±
5%, regardless of the mode of
operation. The supply current is determined by the IC’s
internal bias requirements and the total load current. The
internally required current is a function of the load current
and is shown in Figure 7 for the differential mode.
In the single–ended mode, V
EE
must be –5.0 V,
±
5% in
order to comply with EIA–423–A standards. Figures 12 and
13 indicate the internally required bias currents as a function
of total load current (the sum of the four output loads). The
discontinuity at 0 load current exists due to a change in bias
current when the inputs are switched. The supply currents
vary
≈
±
2.0 mA as V
CC
and V
EE
are varied from
4.75 V
to
5.25 V
.
Sequencing of the supplies during power–up/
power–down is not required.
Bypass capacitors (0.1
μ
F minimum on each supply pin)
are recommended to ensure proper operation. Capacitors
reduce noise induced onto the supply lines by the switching
action of the drivers, particularly where long P.C. board
tracks are involved. Additionally, the capacitors help absorb
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC26LS30DR2G | 功能描述:RS-422接口集成電路 Dual Diff EIA-422-A to Quad EIA-423-A RoHS:否 制造商:Texas Instruments 數據速率: 工作電源電壓:5 V 電源電流:35 mA 工作溫度范圍: 安裝風格:Through Hole 封裝 / 箱體:PDIP-16 封裝:Tube |
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