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參數資料
| 型號： | MC28U512HACA |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MultiMediaCard Specification |
| 中文描述： | 多媒體卡規格 |
| 文件頁數： | 61/66頁 |
| 文件大小： | 1422K |
| 代理商： | MC28U512HACA |
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MultiMediaCard
TM
61
Error
Illegal
Command
Card ECC
Failed
CC Error
‘1’ = error
‘0’ = no error
‘1’ = error
‘0’ = success
‘1’ = failure
‘0’ = no error
‘1’ = error
‘0’ = no error
‘1’ = error
‘0’ = not
protected
‘1’ = protected
‘0’ = no error
‘1’ = error
command failed.
Command not legal for the card
state.
Card internal ECC was applied
but failed to correct the data.
Internal card controller error.
R1 R2
E R
C
R2
DataErr
R2
DataErr
R2
DaraErr
R2
E X
C
E R X
C
C
Error
E R X
A general or an unknown error
occurred during the operation.
Only partial address space was
erased due to existing WP
blocks.
Sequence or password error
during card lock/unlock
operation.
Card is locked by password.
WP Erase Skip
S X
C
Lock/Unlock
Command
R2
E X
C
Card is locked
R2
DaraErr
S X
‘0’ = card is
not locked
‘1’ = card is
locked
‘0’ = cleared
‘1’ = set
A
Erase Retest
R1 R2
S R
An erase sequence was cleared
before exciting because an
output of erase sequence
command was received.
The card enters the idle state
after power up or reset
command. It will exit this state
and become ready upon
completion of this initialization
procedures.
The host is trying to change the
ROM section, or is trying to
reserve the copy bit (set as
original) or permanent WP bit
(unprotected) or the CSD
register.
C
In Idle State
R1 R2
S R
‘0’ = Card is
ready
‘1’ = protected
A
CSD Overwrite
R2
E X
‘0’ = no error
‘1’ = error
C
4.11 SPI Bus Timing
All timing diagrams use the following schematics and abbreviations:
H
L
X
Z
*
busy
Command
Response
Data block
Signal is high (logical ‘1’)
Transmitter bit (Host = ‘1’, Card = ‘0’)
One-cycle pull-up (= ‘1’)
High impedance state (-> = ‘1’)
Repetition
Busy token
Command token
Response token
Data token
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