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參數資料
| 型號： | MC33121FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬傳輸電路 |
| 英文描述： | LOW VOLTAGE SUBSCRIBER LOOP INTERFACE CIRCUIT |
| 中文描述： | TELECOM-SLIC, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 15/32頁 |
| 文件大小： | 570K |
| 代理商： | MC33121FN |
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MC33121
MOTOROLA
15
and VEE. The VEE current (IEE) is nominally 1.0 mA when
on–hook, 8.0 to 12 mA more than the loop current when off–
hook, and
5.0 mA when off–hook but powered down by
using the PDI pin. Ripple and noise rejection from VEE is a
minimum of 40 dB (with a 10
μ
F capacitor at VQB), and is
dependent on the size and quality of the VQB capacitor
(CQB) since VQB is the actual internal supply voltage for the
speech amplifiers. The absolute maximum for VEE is – 60 V,
and should not be exceeded by the combination of the bat-
tery voltage, its tolerance, and its ripple.
VDD is normally supplied from the line card’s digital + 5.0 V
supply, and is referenced to VDG (digital ground). A 0.1
μ
F
capacitor should be provided between VDD and VDG. The
VDD current (IDD) is nominally 1.7 mA when on–hook and
between 6.0 and 8.0 mA when off–hook (see Figure 10).
When the MC33121 is intentionally powered down using the
PDI pin, IDD changes by < 1.0 mA from the normal off–hook
value.
VAG is the analog ground for the MC33121, and is the ref-
erence for the speech signals (RXI and TXO). Current flow is
into
the pin, and is typically < 0.5
μ
A.
Normally, VCC, VDG and VAG are to be at the same DC
level. However, if strong transients are expected at Tip and
Ring, as in a Central Office application, or any application
where the phone line is outdoors, VCC should not be con-
nected directly to VDG and VAG in order to prevent possible
damage to the + 5.0 V system. The MC33121 is designed to
tolerate as much as
±
30 V between VCC and the other two
grounds on a transient basis only. This feature permits VCC
and the other grounds to be kept separate (on an AC basis)
on the line card by transient suppressors, or to be connected
together farther into the system (at the power supplies). See
the Applications Section on ground arrangements and tran-
sient protection for further information on connecting the
MC33121 to the system supplies.
APPLICATIONS INFORMATION
This section contains information on the following topics:
Design Procedure
Power Dissipation Calculations
and Considerations
Selecting the Transistors
Longitudinal Current Capability
PC Board Layout Considerations
Alternate Circuit Configurations
pg. 15
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Design Procedure
This section describes the step–by–step sequence for de-
signing in the MC33121 SLIC into a typical line card applica-
tion for either a PBX or Central Office. The sequence is
important so that each new component value which is calcu-
lated does not affect components previously determined.
Figure 4 (Typical Application Circuit) is the reference circuit
for most of this discussion. The recommended sequence
(detailed below), consists of establishing the DC aspects
first, and then the AC aspects:
1) Determine the maximum loop current for the shortest line,
select RRF. Power dissipation must be considered here.
2) Select the main protection resistors (RP), and diodes,
based on the expected transient voltages. Transient
protection configuration must also be considered here.
3) Select RC based on the expected transient voltages.
4) Select RS based on the desired longitudinal impedance at
Tip and Ring. Transient voltages are also a factor here.
5) Calculate RRO based on the desired AC terminating im-
pedance (return loss).
6) Calculate RRX based on the desired receive gain.
7) Calculate RTX2 and RTX1 based on the desired transmit
gain.
8) Calculate the balance resistor (RB), or network, as ap-
propriate for desired transhybrid rejection.
9) Logic Interface
Preliminary
There is a primary AC feedback loop which has its main
sense points at CP and CN (see Figure 34). The loop ex-
tends from there to TXO, through RRO to RXI, through the
internal amplifiers to the transistor drivers, through RP to Tip
and Ring, and through the RCs to CP and CN. Components
within this loop, such as RP, RC, the transistors, and the
compensation capacitors need not be tightly matched to
each other in order to maintain good longitudinal balance.
The tolerance requirements on these components, and
others, are described in subsequent sections. Any compo-
nents, however, which are placed outside the loop for addi-
tional line card functions, such as test relay contacts, fuses,
resistors in series with Tip and Ring, etc. will affect longitu-
dinal balance, signal balance, and gains if their values and
mismatch is not carefully considered. The MC33121 cannot
compensate for mismatch among components outside the
loop.
The compensation capacitors (0.01
μ
F) shown at the tran-
sistor collectors (Figure 4) compensate the transistor driver
amplifiers, providing the required loop stability. The required
tolerance on these capacitors can be determined from the
following guidelines:
A 10% mismatch (
±
5% tolerance) will degrade the longi-
tudinal balance by
1.0 dB on a 60 dB device, and by
3.0 dB on a 70 dB device.
A 20% mismatch (
±
10% tolerance) will degrade the longi-
tudinal balance by
3.0 dB on a 60 dB device, and by
6.0 dB on a 70 dB device.
High quality ceramic capacitors are recommended since
they serve the secondary function of providing a bleedoff
path for RF signals picked up on the phone line. These
capacitors should be connected to a good quality RF ground.
The capacitors used at CQB and CF must be low leakage
to obtain proper performance. Leakage at the CQB capacitor
will affect the DC loop current characteristics, while leakage
at the CF capacitor will affect the AC gain parameters, and
possibly render the IC inoperative.
1) Maximum Loop Current and Battery Feed Resistance
The maximum loop current (at RL = 0) is determined by the
RRF resistor between RFO and RXI. The current limit is ac-
complished by three internal series diodes (see Figure 27)
which clamp the voltage across RRF as the loop resistance
decreases, thereby limiting the current at RXI. Since the loop
current is 102 x IRXI, the loop current is therefore clamped.
The graphs of Figures 5 to 7 indicate the maximum loop
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