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參數資料
| 型號： | MC34055DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 網絡接口 |
| 英文描述： | 5-V Battery-Backup Supervisors for RAM Retention 8-MSOP -40 to 85 |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PDSO24 |
| 封裝： | PLASTIC, SO-24 |
| 文件頁數： | 10/16頁 |
| 文件大小： | 280K |
| 代理商： | MC34055DW |
MC34055
10
MOTOROLA ANALOG IC DEVICE DATA
Figure 9. Differential Receiver Media Interface Circuitry
RX+
ZF
ZO
RX–
ZF
Pulse
Transformer
Twisted Pair
RT
16
15
Where: RT is a terminating resistor (100
),
Where:
ZF is the filters impedance, and ZO is the
Where:
characteristic impedance of the twisted pair (100
).
The MC34055 powers up in a squelched and “link OK”
state, after which minimum and maximum link test and
maximum link fail timers are started. If valid data or a link
pulse is received after the link test minimum timer but before
the link fail maximum timer times out, the timers are reset and
begin counting again. In the event of missing or incorrect link
pulses, the MC34055 enters the link fail state whereby the
LNKFL H status pin is asserted until valid data or link pulse
activity appears at the receiver terminals.
Powering up in the squelched state assures that the data
path to the data output pin (RX Data A/B) is disabled, and
prevents noise at the receiver terminals (RX+/RX–), from
being interpreted as valid input data. Once transitions appear
at the receiver terminals, the smart squelch circuitry checks
for the smart squelch requirements to unsquelch; an
alternating sequence (1010... or 0101...) of pulses with
amplitude of at least 525 mV. This requirement is met by the
preamble of an IEEE 802.3 frame with good signal to noise
ratio.
After a pulse is received and checked for proper polarity
and amplitude, the pulse width is checked for proper
duration. If the duration is to short or too long the smart
squelch circuitry resets and begins to look again for a proper
sequence. By requiring the differential pulses to meet
amplitude and sequence requirements, it is unlikely that
pulses due to crosstalk from coresident twisted pairs are
capable of causing the receiver to unsquelch. If a positive
pulse is received first and the differential driver is not
transmitting, the receiver should unsquelch after three
alternating pulses. If a negative pulse is received first, one
additional pulse is required before unsquelch. If the
differential driver is transmitting, three additional pulses are
required to unsquelch.
After meeting the smart squelch requirements, the
MC34055 will pull high the RX EN H pin and enable the path
to the receive data pin (RX Data A/B) provided the MC34055
is not in the loop back test mode (Loop L low). If the receiver
unsquelches, the receive enable pin remains high and the
data path to the receive data pin remains enabled until
transitions cease to exist at the receiver terminals. Valid data
reception is also indicated by high/low transitions of the
LNKFL H pin at 100 ms intervals. When transitions at the
differential terminals cease, marking the end of frame activity,
the receiver re–enters the squelch state, pulls low on the RX
EN H pin, and begins accepting valid link pulses until the start
of the next 802.3 frame.
If the MC34055 is requested to begin transmitting (TX EN
H is asserted), and the receiver unsquelches simultaneously,
there is a collision. Also, if the MC34055 driver enable pin is
previously asserted and the receiver detects valid transition
activity, the receiver Smart Squelch circuitry verifies the
possibility of collision by requiring three extra transitions at
the differential receiver before the unsquelch condition is
reached. If unsquelch occurs, a collision condition exists.
During all collision conditions the MC34055 asserts the CTL
H status pin for the duration of the condition and for a time
after the end of collision.
During a collision condition the receive and transmit paths
are still both enabled allowing transparency to the media.
Either the presence of simultaneous transmit and receive
activity or the condition of the CTL H status pin can be used
by the communications controller to acknowledge and react
to the collision. In applications where a 10 MHz collision
signal is required by an SIA, the combination of this status pin
and the clock oscillator output can be logically combined to
provide a 10 MHz output. If the DTE reacts to the collision
and ceases transmitting, the MC34055 will decay to idle until
a re–transmit is attempted.
Crystal Oscillator
The MC34055 has an on–chip clock oscillator used to
provide a reliable and accurate time reference to all the
internal timers. The oscillator can be run with a crystal or
driven at Pin 24 from an external clock source. Also provided
is a buffered clock output which is useful if the MC34055 is to
be used in a repeater or concentrator application.
Table 1. The crystal used in the oscillator is subject to the following specifications.
Crystal Operating Mode
Fundamental
Crystal Cut Type
AT
Crystal External Shunt Capacitance
7.0 pF Max
Crystal Resonant Mode
Series
Crystal Accuracy
±
0.01% @ 25
°
C
Crystal Temperature Variance
0.005% from 0
°
to 70
°
C
Crystal Series Resistance
25
Max, 17
Typical
Crystal Operating Temperature Range
0
°
to 70
°
C
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