- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371043 > MC68332AVFC16 (MOTOROLA INC) 32-Bit Modular Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68332AVFC16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit Modular Microcontroller |
| 中文描述： | 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 78/88頁(yè) |
| 文件大小： | 446K |
| 代理商： | MC68332AVFC16 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)當(dāng)前第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)
MOTOROLA
78
MC68332
MC68332TS/D
Command RAM is used by the QSPI when in master mode. The CPU writes one byte of control infor-
mation to this segment for each QSPI command to be executed. The QSPI cannot modify information
in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select
field enables peripherals for transfer. The command control field provides transfer options.
A maximum of 16 commands can be in the queue. Queue execution by the QSPI proceeds from the
address in NEWQP through the address in ENDQP. (Both of these fields are in SPCR2.)
CONT — Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
BITSE — Bits per Transfer Enable
0 = 8 bits
1 = Number of bits set in BITS field of SPCR0
DT — Delay after Transfer
The QSPI provides a variable delay at the end of serial transfer to facilitate the interface with peripherals
that have a latency requirement. The delay between transfers is determined by the SPCR1 DTL field.
DSCK — PCS to SCK Delay
0 = PCS valid to SCK transition is one-half SCK.
1 = SPCR1 DSCKL field specifies delay from PCS valid to SCK.
PCS[3:0] — Peripheral Chip Select
Use peripheral chip-select bits to select an external device for serial data transfer. More than one pe-
ripheral chip select can be activated at a time, and more than one peripheral chip can be connected to
each PCS pin, provided that proper fanout is observed.
SS — Slave Mode Select
Initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault
will be generated.
6.5.4 Operating Modes
The QSPI operates in either master or slave mode. Master mode is used when the MCU originates data
transfers. Slave mode is used when an external device initiates serial transfers to the MCU through the
QSPI. Switching between the modes is controlled by MSTR in SPCR0. Before entering either mode,
appropriate QSM and QSPI registers must be properly initialized.
In master mode, the QSPI executes a queue of commands defined by control bits in each command
RAM queue entry. Chip-select pins are activated, data is transmitted from transmit RAM and received
into receive RAM.
In slave mode, operation proceeds in response to SS pin activation by an external bus master. Opera-
tion is similar to master mode, but no peripheral chip selects are generated, and the number of bits
transferred is controlled in a different manner. When the QSPI is selected, it automatically executes the
next queue transfer to exchange data with the external device correctly.
Although the QSPI inherently supports multimaster operation, no special arbitration mechanism is pro-
vided. A mode fault flag (MODF) indicates a request for SPI master arbitration. System software must
provide arbitration. Note that unlike previous SPI systems, MSTR is not cleared by a mode fault being
set, nor are the QSPI pin output drivers disabled. The QSPI and associated output drivers must be dis-
abled by clearing SPE in SPCR1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68332CFC16 | 32-Bit Modular Microcontroller |
| MC68332CFC20 | 32-Bit Modular Microcontroller |
| MC68332MFC16 | 32-Bit Modular Microcontroller |
| MC68332MFC20 | 32-Bit Modular Microcontroller |
| MC68332TS | 32-Bit Modular Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68332AVFC20 | 制造商:Rochester Electronics LLC 功能描述:32BIT MCU,2KRAM,TPU,QSM - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC68332AVFV16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332AVFV20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332CFC16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332CFC20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。