- 您現在的位置：買賣IC網 > PDF目錄371043 > MC68332MFC20 (MOTOROLA INC) 32-Bit Modular Microcontroller PDF資料下載
參數資料
| 型號： | MC68332MFC20 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-Bit Modular Microcontroller |
| 中文描述： | 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數： | 40/88頁 |
| 文件大小： | 446K |
| 代理商： | MC68332MFC20 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
MOTOROLA
40
MC68332
MC68332TS/D
3.7.3 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512
cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert
RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for ten cy-
cles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one,
reset exception processing begins. If, however, the reset input is at logic level zero, the reset control
logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-
impedance state for ten cycles, then it is tested again. The process repeats until RESET is released.
3.7.4 Power-On Reset
When the SIM clock synthesizer is used to generate the system clock, power-on reset involves special
circumstances related to application of system and clock synthesizer power. Regardless of clock
source, voltage must be applied to clock synthesizer power input pin V
DDSYN
in order for the MCU to
operate. The following discussion assumes that V
DDSYN
is applied before and during reset. This mini-
mizes crystal start-up time. When V
DDSYN
is applied at power-on, start-up time is affected by specific
crystal parameters and by oscillator circuit design. V
DD
ramp-up time also affects pin state during reset.
During power-on reset, an internal circuit in the SIM drives the internal (IMB) and external reset lines.
The circuit releases the internal reset line as V
DD
ramps up to the minimum specified value, and SIM
pins are initialized. When V
DD
reaches the specified minimum value, the clock synthesizer VCO begins
operation. Clock frequency ramps up to the specified limp mode frequency. The external RESET line
remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal reset signal is asserted for four clock cycles, these modules reset. V
DD
ramp time and
VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15
milliseconds. During this period, module port pins may be in an indeterminate state. While input-only
pins can be put in a known state by means of external pull-up resistors, external logic on input/output
or output-only pins must condition the lines during this time. Active drivers require high-impedance buff-
ers or isolation resistors to prevent conflict.
3.7.5 Use of Three State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,
high-impedance state. The signal must remain asserted for ten clock cycles in order for drivers to
change state. There are certain constraints on use of TSC during power-on reset:
When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-
up time affects how long the ten cycles take. Worst case is approximately 20 milliseconds from TSC
assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to high-imped-
ance state as soon after TSC assertion as ten clock pulses have been applied to the EXTAL pin.
相關PDF資料 |
PDF描述 |
|---|---|
| MC68332TS | 32-Bit Modular Microcontroller |
| MC68332GCFC16 | 32-Bit Modular Microcontroller |
| MC68332GCFC20 | 32-Bit Modular Microcontroller |
| MC68332GCFV20 | 32-Bit Modular Microcontroller |
| MC68332GCFVV16 | 32-Bit Modular Microcontroller |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68332MFV16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332MFV20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332TS | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332VFC16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
| MC68332VFC20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32-Bit Modular Microcontroller |
發布緊急采購，3分鐘左右您將得到回復。