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參數(shù)資料
| 型號(hào)： | MC68HC11E20CFN2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 27/268頁(yè) |
| 文件大小： | 3696K |
| 代理商： | MC68HC11E20CFN2 |
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General Description
Pin Descriptions
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
General Description
27
The V
STBY
pin is used to input random-access memory (RAM) standby power.
When the voltage on this pin is more than one MOS threshold (about 0.7 volts)
above the V
DD
voltage, the internal RAM and part of the reset logic are powered
from this signal rather than the V
DD
input. This allows RAM contents to be retained
without V
DD
power applied to the MCU. Reset must be driven low before V
DD
is
removed and must remain low until V
DD
has been restored to a valid level.
1.4.7.1 V
RL
and V
RH
These two inputs provide the reference voltages for the analog-to-digital (A/D)
converter circuitry:
V
RL
is the low reference, typically 0 Vdc.
V
RH
is the high reference.
For proper A/D converter operation:
V
RH
should be at least 3 Vdc greater than V
RL
.
V
RL
and V
RH
should be between V
SS
and V
DD
.
1.4.8 STRA/AS
The strobe A (STRA) and address strobe (AS) pin performs either of two separate
functions, depending on the operating mode:
In single-chip mode, STRA performs an input handshake (strobe input)
function.
In the expanded multiplexed mode, AS provides an address strobe function.
AS can be used to demultiplex the address and data signals at port C. Refer to
Section 2. Operating Modes and On-Chip Memory
.
1.4.9 STRB/R/W
The strobe B (STRB) and read/write (R/W) pin act as either an output strobe or as
a data bus direction indicator, depending on the operating mode.
In single-chip operating mode, STRB acts as a programmable strobe for
handshake with other parallel devices. Refer to
Section 6. Parallel Input/Output
(I/O) Ports
for further information.
In expanded multiplexed operating mode, R/W is used to indicate the direction of
transfers on the external data bus. A low on the R/W pin indicates data is being
written to the external data bus. A high on this pin indicates that a read cycle is in
progress. R/W stays low during consecutive data bus write cycles, such as a
double-byte store. It is possible for data to be driven out of port C, if internal read
visibility (IRV) is enabled and an internal address is read, even though R/W is in a
high-impedance state. Refer to
Section 2. Operating Modes and On-Chip
Memory
for more information about IRVNE (internal read visibility not E).
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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