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| 型號(hào)： | MC68HC11E9CFN3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers |
| 中文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 30/268頁(yè) |
| 文件大小： | 3696K |
| 代理商： | MC68HC11E9CFN3 |
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General Description
Data Sheet
M68HC11E Family — Rev. 5
30
General Description
MOTOROLA
1.4.10.2 Port B
During single-chip operating modes, all port B pins are general-purpose output
pins. During MCU reads of this port, the level sensed at the input side of the port B
output drivers is read. Port B can also be used in simple strobed output mode. In
this mode, an output pulse appears at the STRB signal each time data is written to
port B.
In expanded multiplexed operating modes, all of the port B pins act as high order
address output signals. During each MCU cycle, bits 15–8 of the address bus are
output on the PB7–PB0 pins. The PORTB register is treated as an external
address in expanded modes.
1.4.10.3 Port C
While in single-chip operating modes, all port C pins are general-purpose I/O pins.
Port C inputs can be latched into an alternate PORTCL register by providing an
input transition to the STRA signal. Port C can also be used in full handshake
modes of parallel I/O where the STRA input and STRB output act as handshake
control lines.
When in expanded multiplexed modes, all port C pins are configured as
multiplexed address/data signals. During the address portion of each MCU cycle,
bits 7–0 of the address are output on the PC7–PC0 pins. During the data portion
of each MCU cycle (E high), PC7–PC0 are bidirectional data signals,
DATA7–DATA0. The direction of data at the port C pins is indicated by the R/W
signal.
The CWOM control bit in the PIOC register disables the port C P-channel output
driver. CWOM simultaneously affects all eight bits of port C. Because the
N-channel driver is not affected by CWOM, setting CWOM causes port C to
become an open-drain type output port suitable for wired-OR operation.
In wired-OR mode:
When a port C bit is at logic level 0, it is driven low by the N-channel driver.
When a port C bit is at logic level 1, the associated pin has high-impedance,
as neither the N-channel nor the P-channel devices are active.
It is customary to have an external pullup resistor on lines that are driven by
open-drain devices. Port C can only be configured for wired-OR operation when
the MCU is in single-chip mode. Refer to
Section 6. Parallel Input/Output (I/O)
Ports
for additional information about port C functions.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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