- 您現在的位置：買賣IC網 > PDF目錄371049 > MC68HC11E9FN3 (MOTOROLA INC) Microcontrollers PDF資料下載
參數資料
| 型號： | MC68HC11E9FN3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers |
| 中文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 137/268頁 |
| 文件大小： | 3696K |
| 代理商： | MC68HC11E9FN3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁當前第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁
Serial Peripheral Interface (SPI)
SPI System Errors
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
137
between successive SPI characters. In cases where there is only one SPI slave
MCU, its SS line can be tied to V
SS
as long as only CPHA = 1 clock mode is used.
8.6 SPI System Errors
Two system errors can be detected by the SPI system. The first type of error arises
in a multiple-master system when more than one SPI device simultaneously tries
to be a master. This error is called a mode fault. The second type of error, write
collision, indicates that an attempt was made to write data to the SPDR while a
transfer was in progress.
When the SPI system is configured as a master and the SS input line goes to active
low, a mode fault error has occurred — usually because two devices have
attempted to act as master at the same time. In cases where more than one device
is concurrently configured as a master, there is a chance of contention between
two pin drivers. For push-pull CMOS drivers, this contention can cause permanent
damage. The mode fault mechanism attempts to protect the device by disabling the
drivers. The MSTR control bit in the SPCR and all four DDRD control bits
associated with the SPI are cleared and an interrupt is generated subject to
masking by the SPIE control bit and the I bit in the CCR.
Other precautions may need to be taken to prevent driver damage. If two devices
are made masters at the same time, mode fault does not help protect either one
unless one of them selects the other as slave. The amount of damage possible
depends on the length of time both devices attempt to act as master.
A write collision error occurs if the SPDR is written while a transfer is in progress.
Because the SPDR is not double buffered in the transmit direction, writes to SPDR
cause data to be written directly into the SPI shift register. Because this write
corrupts any transfer in progress, a write collision error is generated. The transfer
continues undisturbed, and the write data that caused the error is not written to the
shifter.
A write collision is normally a slave error because a slave has no control over when
a master initiates a transfer. A master knows when a transfer is in progress, so
there is no reason for a master to generate a write-collision error, although the SPI
logic can detect write collisions in both master and slave devices.
The SPI configuration determines the characteristics of a transfer in progress. For
a master, a transfer begins when data is written to SPDR and ends when SPIF is
set. For a slave with CPHA equal to 0, a transfer starts when SS goes low and ends
when SS returns high. In this case, SPIF is set at the middle of the eighth SCK
cycle when data is transferred from the shifter to the parallel data register, but the
transfer is still in progress until SS goes high. For a slave with CPHA equal to 1,
transfer begins when the SCK line goes to its active level, which is the edge at the
beginning of the first SCK cycle. The transfer ends in a slave in which CPHA
equals 1 when SPIF is set.
F
Freescale Semiconductor, Inc.
n
.
相關PDF資料 |
PDF描述 |
|---|---|
| MC68HC11E9FU3 | Microcontrollers |
| MC68HC11E9MPB2 | Microcontrollers |
| MC68HC11E9VB2 | Microcontrollers |
| MC68HC11E1CFN2 | Microcontrollers |
| MC68HC11E0CFN2 | Microcontrollers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68HC11E9FU3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC68HC11E9MB2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC68HC11E9MFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC68HC11E9MFU2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC68HC11E9MPB2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
發布緊急采購，3分鐘左右您將得到回復。