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參數(shù)資料
| 型號(hào)： | MC74F74D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP FAST SCHOTTKY TTL |
| 中文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | SOIC-14 |
| 文件頁(yè)數(shù)： | 1/3頁(yè) |
| 文件大小： | 63K |
| 代理商： | MC74F74D |
4-33
FAST AND LS TTL DATA
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The MC54/74F74 is a dual D-type flip-flop with Direct Clear and Set inputs
and complementary (Q, Q) outputs. Information at the input is transferred to
the outputs on the positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
ESD >4000 Volts
13
14
12
11
10
9
8
2
1
3
4
5
6
7
GND
VCC
CD2
D2
CP2
SD2
Q2
Q2
CD1
D1
CP1
SD1
Q1
Q1
CONNECTION DIAGRAM
CP1
D1
SD1
CD1
Q1
Q1
D2
CP2
CD2
SD2
Q2
Q2
FUNCTION TABLE (Each Half)
Input
Outputs
@ tn
D
@ tn + 1
Q
Q
L
L
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
D
SUFFIX
SOIC
CASE 751A-02
MC54FXXJ
MC74FXXN
MC74FXXD
Ceramic
Plastic
SOIC
MC54/74F74
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
FAST
SCHOTTKY TTL
14
1
14
1
ORDERING INFORMATION
14
1
LOGIC SYMBOL
4
5
6
3
2
1
10
12
11
8
9
13
VCC = PIN 14
GND = PIN 7
SD1
D1
CP1
Q1
Q1
CD1
SD2
D2
CP2
Q2
Q2
CD2
Asynchronous Inputs:
LOW Input to SD sets Q to HIGH level
LOW Input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
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