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參數資料
| 型號： | MC74HC16xADR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable Counters |
| 中文描述： | 可預置計數器 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 284K |
| 代理商： | MC74HC16XADR2 |
MC74HC161A, MC74HC163A
http://onsemi.com
4
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable.
See Applications information in this data sheet.
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Parameter
Maximum Clock Frequency (50% Duty Cycle)*
1, 7
2.0
4.5
6.0
30
35
V
6
25 C
5
24
28
20
24
MHz
20
16
23
20
28
22
4
tPLH
Maximum Propagation Delay, Clock to Q
4.5
6.0
22
18
2.0
25
20
120
30
23
160
120
200
tPHL
4.5
6.0
20
2.0
22
145
25
185
135
220
tPHL
Maximum Propagation Delay, Reset to Q (HC161A Only)
4.5
2.0
145
185
135
220
Maximum Propagation Delay, Enable T to Ripple Carry Out
4.5
16
150
115
18
20
4.5
18
175
130
20
22
Maximum Propagation Delay, Clock to Ripple Carry Out
4.5
22
160
135
27
30
3.0
4.5
100
22
135
28
150
35
Maximum Propagation Delay, Reset to Ripple Carry Out
(HC161A Only)
13
3.0
16
120
19
140
155
6.0
3.0
30
40
55
Typical @ 25
°
C, VCC = 5.0 V
45
CPD
Power Dissipation Capacitance (Per Gate)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
pF
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