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參數(shù)資料
| 型號： | MC74HC259N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Addressable Latch 1-of-8 Decoder |
| 中文描述： | HC/UH SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 199K |
| 代理商： | MC74HC259N |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
! !
High–Performance Silicon–Gate CMOS
The MC54/74HC259 is identical in pinout to the LS259. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC259 has four modes of operation as shown in the mode selection
table. In the addressable latch mode, the data on Data In is written into the
addressed latch. The addressed latch follows the data input with all
non–addressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous state and are unaffected by the
Data or Address inputs. In the one–of–eight decoding or demultiplexing
mode, the addressed output follows the state of Data In with all other outputs
in the LOW state. In the Reset mode all outputs are LOW and unaffected by
the address and data inputs. When operating the HC259 as an addressable
latch, changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the memory
mode.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 202 FETs or 50.5 Equivalent Gates
LOGIC DIAGRAM
ADDRESS
INPUTS
A0
A1
A2
DATA IN
RESET
ENABLE
14
15
13
3
2
1
12
11
10
9
7
6
5
4Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 16 = VCC
PIN 8 = GND
NONINVERTING
OUTPUTS
PIN ASSIGNMENT
LATCH SELECTION TABLE
Address Inputs
C
B
Latch
Addressed
A
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MODE SELECTION TABLE
Enable
Reset
Mode
L
H
L
H
H
H
L
L
Addressable Latch
Memory
8–Line Demultiplexer
Reset
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
Q7
DATA IN
ENABLE
RESET
VCC
Q4
Q5
Q6
Q0
A2
A1
A0
GND
Q3
Q2
Q1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
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| MC74HC273ADTR2G | 功能描述:觸發(fā)器 2-6V CMOS Octal D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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