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參數資料
| 型號： | MC74HC299DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Bidirectional Universal Shift Register with Parallel I/O |
| 中文描述： | HC/UH SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-20 |
| 文件頁數： | 5/8頁 |
| 文件大小： | 268K |
| 代理商： | MC74HC299DW |
MC74HC299
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5
MOTOROLA
FUNCTION TABLE
Inputs
Response
Mode
Reset
Mode
Select
Output
Enables
Clock
Serial
Inputs
PA/QA
PB/QB
PC/QC
PD/QD
PE/QE
PF/QF
PG/QG
PH/QH
S2
S1
OE1
OE2
DA
DH
QA
′
QH
′
Reset
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
QA through QH = Z
Shift
Right
H
H
H
L
L
L
H
H
H
H
X
L
X
H
L
D
D
D
X
X
X
Shift Right: QA through QH = Z; DA
Shift Right: QA through QH = Z; DA
Shift Right: DA
FA = QA; FA
FA; FA
FA; FA
FB; etc.
FB; etc.
D
D
D
QG
QG
QG
FB = QB; etc.
Shift
Left
H
H
H
H
H
H
L
L
L
H
X
L
X
H
L
X
X
X
D
D
D
Shift Left: QA through QH = Z; DH
Shift Left: QA through QH = Z; DH
Shift Left: DH
FH = QH; FH
FH; FH
FH; FH
FG = QG; etc.
FG; etc.
FG; etc.
QB
QB
QB
D
D
D
Parallel
Load
H
H
H
X
X
X
X
Parallel Load: PN
FN
PA
PH
Hold
H
H
H
L
L
L
L
L
L
H
X
L
X
H
L
X
X
X
X
X
X
X
X
X
Hold: QA through QH = Z; FN = FN
Hold: QA through QH = Z; FN = FN
Hold: QN = QN
PA
PA
PA
PH
PH
PH
Z = high impedance
D = data on serial input
F = flip–flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high impedance state, however, sequential
operation or clearing of the register is not affected.
PIN DESCRIPTIONS
DATA INPUTS
SA (Pin 11)
Serial data input (Shift Right). Data on this input is shifted
into the shift register on the rising edge of Clock when S2 is
low and S1 is high (shift right mode).
SH (Pin 18)
Serial data input (Shift Left). Data on this input is shifted
into the shift register on the rising edge of Clock when S2 is
high and S1 is low (shift left mode).
PA through PH (Pins 7, 13, 6, 14, 5, 15, 4, 16)
Parallel data port inputs. Data on these pins can be paral-
lel loaded into the shift register on the rising edge of Clock
when both S1 and S2 are high. For any other combination of
S1 and S2, these pins serve as the outputs of the shift
register.
CONTROL INPUTS
Clock (Pin 12)
Clock input. A low–to–high transition on this pin shifts the
data at each stage to the next stage (shift right or left mode)
or loads the data at the parallel data inputs into the shift reg-
ister (parallel load mode).
OE1, OE2 (Pins 2, 3)
Active–low output enables. When both OE1 and OE2 are
low, the Outputs QA through QH are enabled. When one or
both output enables are high, the outputs are forced to the
high–impedance state; however, sequential operation or
clearing of the register is not affected.
Reset (Pin 9)
Active–low reset. A low on this pin resets all stages of the
register to a low level. The reset operation is asynchronous.
S1, S2 (Pins 1, 19)
Mode select inputs. The levels present at these pins deter-
mine the shift register’s mode of operation:
S1 = S2 = Low. Hold.
S1 = Low, S2 High. Shift left.
S1 = High, S2 Low. Shift right.
S1 = S2 = High. Parallel load.
OUTPUTS
QA
′
, QH
′
(Pins 8, 17)
Serial data outputs. These are the outputs of the first and
last stages of the shift register, respectively. These outputs
are not 3–state outputs and have standard drive capabilities.
QA through QH (Pins 7, 13, 6, 14, 5, 15, 4, 16)
Parallel data port outputs. Shifted data is present at these
pins when OE1 and OE2 are low. For all other combinations
of OE1 and OE2 these outputs are in the high–impedance
state.
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