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參數(shù)資料
| 型號： | MC74HC4053ADR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | Quad Comparator; Package: SOP; No of Pins: 14; Container: Rail |
| 中文描述： | TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 451K |
| 代理商： | MC74HC4053ADR2 |
MC54/74HC4051 MC74HC4052 MC54/74HC4053
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
6
ADDITIONAL APPLICATION CHARACTERISTICS
(GND = 0 V)
Symbol
Parameter
Condition
V
V
Limit*
Unit
VCC
VEE
25
°
C
BW
Maximum On–Channel Bandwidth
(Figure 6)
fin = 1MHz Sine Wave; Adjust fin Voltage to
RL = 50
, CL = 10pF
6.00
‘51
‘52
‘53
MHz
or Minimum Frequency Response
Obtain 0dBm at VOS; Increase fin Frequency
Until dB Meter Reads –3dB;
2.25
4.50
–2.25
–4.50
–6.00
80
80
80
95
95
95
120
120
120
—
Off–Channel Feedthrough Isolation
(Figure 7)
fin = Sine Wave; Adjust fin Voltage to Obtain
0dBm at VIS
fin = 10kHz, RL = 600
, CL = 50pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
–50
–50
–50
dB
fin = 1.0MHz, RL = 50
, CL = 10pF
Vin
≤
1MHz Square Wave (tr = tf = 6ns);
Adjust RL at Setup so that IS = 0A;
Enable = GND
2.25
4.50
6.00
–2.25
–4.50
–6.00
–40
–40
–40
—
Feedthrough Noise.
Channel–Select Input to Common
I/O (Figure 8)
RL = 600
, CL = 50pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
25
105
135
mVPP
RL = 10k
, CL = 10pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
35
145
190
—
Crosstalk Between Any Two
Switches (Figure 12)
(Test does not apply to HC4051)
fin = Sine Wave; Adjust fin Voltage to Obtain
0dBm at VIS
fin = 10kHz, RL = 600
, CL = 50pF
2.25
4.50
6.00
–2.25
–4.50
–6.00
–50
–50
–50
dB
fin = 1.0MHz, RL = 50
, CL = 10pF
fin = 1kHz, RL = 10k
, CL = 50pF
THD = THDmeasured – THDsource
VIS = 4.0VPP sine wave
VIS = 8.0VPP sine wave
VIS = 11.0VPP sine wave
2.25
4.50
6.00
–2.25
–4.50
–6.00
–60
–60
–60
THD
Total Harmonic Distortion
(Figure 14)
2.25
4.50
6.00
–2.25
–4.50
–6.00
0.10
0.08
0.05
%
* Limits not tested. Determined by design and verified by qualification.
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