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參數資料
| 型號： | MC74HC597D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch |
| 中文描述： | HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-16 |
| 文件頁數： | 4/11頁 |
| 文件大小： | 291K |
| 代理商： | MC74HC597D |
MC54/74HC597A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs is stored in the
input latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input it Serial
Shift/Parallel Load is high. Data on this input is ignored when
Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied to
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the input latch, and serial shifting
is inhibited.
Reset (Pin 10)
Asynchronous, Active–low shift register reset. A low level
applied to this input resets the shift register to a low level, but
does not change the data in the input latch.
Shift Clock (Pin 11)
Serial shift register clock. A low–to–high transition on this
input shifts data on the Serial Data Input into the shift register
and data in stage H is shifted out QH, being replaced by the
data previously stored in stage G.
Latch Clock (Pin 12)
Latch clock. A low–to–high transition on this input loads
the parallel data on inputs A–H into the input latch.
OUTPUT
QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register.
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