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參數資料
| 型號： | MC74HC75D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 2-Bit Transparent Latch |
| 中文描述： | HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數： | 3/5頁 |
| 文件大小： | 172K |
| 代理商： | MC74HC75D |
MC74HC75
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 5)
4.5
6.0
25
21
38
32
tPLH,
Maximum Propagation Delay, D to Q
2.0
110
140
31
26
165
ns
tPHL
(Figures 2 and 5)
4.5
6.0
29
25
44
38
tPLH,
Maximum Propagation Delay, Latch Enable to
Q
2.0
125
155
36
31
190
ns
tTHL
(Figures 3 and 5)
4.5
6.0
15
13
22
19
Cin
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
19
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Latch)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
35
pF
Symbol
Parameter
V
25 C
Unit
(Figure 4)
4.5
20
85 C
125 C
30
ns
6.0
5
25
(Figure 4)
4.5
16
6
24
7
ns
6.0
400
400
20
400
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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