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參數資料
| 型號： | MC74HCT157AN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad 2-Input Data Selector/Multiplexer with LSTTL-Compatible Inputs |
| 中文描述： | HCT SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16 |
| 封裝： | 648-08 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 127K |
| 代理商： | MC74HCT157AN |
SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1997
2/97
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High–Performance Silicon–Gate CMOS
The MC74HCT157A is identical in pinout to the LS157. This device may
be used as a level converter for interfacing TTL or NMOS outputs to High
Speed CMOS inputs.
This device routes 2 nibbles (A or B) to a single port (Y) as determined by
the Select input. The data is presented at the outputs in noninverted form. A
high level on the Output Enable input sets all four Y outputs to a low level.
The HCT157A is similar in function to the HC257 which has 3–state
outputs.
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
μ
A
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 102 FETs or 25.5 Equivalent Gates
LOGIC DIAGRAM
2
5
11
14
3
6
10
13
4
7
9
12
1
15
A0
A1
A2
A3
B0
B1
B2
B3
Y0
Y1
Y2
Y3
SELECT
OUTPUT ENABLE
DATA
OUTPUTS
NIBBLE
A INPUTS
NIBBLE
B INPUTS
PIN 16 = VCC
PIN 8 = GND
* Equivalent to a two input NAND gate.
Internal Gate Count*
Design Criteria
25.5
Value
ea
Unit
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Output
Enable
H
L
L
Outputs
Y0 – Y3
L
A0–A3
B0–B3
Select
X
L
H
X = don’t care
A0 – A3, B0 – B3 = the levels
of the respective Data–Word
Inputs.
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
SELECT
Y0
B0
A0
Y1
B1
A1
GND
Y3
B3
A3
OUTPUT
ENABLE
VCC
B2
A2
Y2
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
1
16
ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXAD
Plastic
SOIC
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