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參數資料
| 型號： | MC88PL117FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CMOS PLL CLOCK DRIVER |
| 中文描述： | 88PL SERIES, PLL BASED CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 9/11頁 |
| 文件大小： | 139K |
| 代理商： | MC88PL117FN |
MC88PL117
TIMING SOLUTIONS
BR1333 — Rev 6
9
MOTOROLA
88PL117
2X_Q
Output
Rs
ZO (CLOCK TRACE)
MPC601
2X_PCLK
Input
Rs = Zo – 7
Rp = 1.5 Zo
Rp
Figure 11. MPC601 2X_PCLK Input Termination Scheme
Figure 12. Recommended Loop Filter and Analog Isolation Scheme
47
BOARD VCC
0.1
μ
F (LOOP
FILTER CAP)
330
470K
0.1
μ
F HIGH
FREQ
BYPASS
10
μ
F LOW
FREQ BYPASS
47
BOARD GND
ANALOG VCC
FIL
ANALOG GND
ANALOG LOOP FILTER/VCO
SECTION
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDELINES
IS ALL THAT IS NECESSARY TO USE THE MC88PL117 IN A NORMAL
DIGITAL ENVIRONMENT.
Notes Concerning Loop Filter and Board Layout Issues
1 Figure 12 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
1aAll loop filter and analog isolation components should
be tied as close to the package as possible. Stray
current passing through the parasitics of long traces
can cause undesirable voltage transients at the FIL pin.
1bThe 47
resistors, the 10
μ
F low frequency bypass
capacitor, and the 0.1
μ
F high frequency bypass
capacitor form a wide bandwidth filter that will minimize
the PLL’s sensitivity to voltage transients from the
system digital VCC supply and ground planes. This filter
will typically ensure that a 100mV step deviation on the
digital VCC supply will cause no more than a 100pS
phase deviation on the device outputs. A 250mV step
deviation on VCC using the recommended filter values
should cause no more than a 250pS phase deviation; if
a 25
μ
F bypass capacitor is used (instead of 10
μ
F) a
250mV VCC step should cause no more than a 100pS
phase deviation. If good bypass techniques are used
on a board design near components which may cause
digital VCC and ground noise, the above described VCC
step deviations should not occur at the digital VCC
supply. The purpose of the bypass filtering scheme
shown in Figure 12 is to give the chip additional
protection from the power supply and ground plane
transients that can occur in a a high frequency, high
speed digital system.
1cThere are no special requirements set forth for the loop
filter resistors (470K and 330
). The loop filter
capacitor (0.1
μ
F) can be a ceramic chip capacitor, the
same as a standard bypass capacitor.
2 In addition to the bypass capacitors used in the analog
filter of Figure 12, there should be a 0.1
μ
F bypass
capacitor between each of the other (digital) nine VCC pins
and the board ground plane. This will reduce output
switching noise caused by the high current outputs, in
addition to reducing potential for noise in the ‘analog’
section of the chip. These bypass capacitors should also
be tied as close to the package as possible.
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