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參數(shù)資料
| 型號(hào)： | MC92300 |
| 廠商： | Motorola, Inc. |
| 英文描述： | VITERBI Decoder for Digital TV |
| 中文描述： | 維特比譯碼數(shù)字電視 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 42K |
| 代理商： | MC92300 |
MOTOROLA, INC. 1997
5/28/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Current Information@www.mot.com/ADC
Product Preview
VITERBI Decoder for Digital TV
This product preview describes a high performance device, a Viterbi Decoder, for
Digital-TV applications according to the EBU defined DVB transmission standard for
satellite and cable Set-Top systems.
Viterbi Decoder - Capability Specification
Operates at max. 50MBits/s output rate to work with all present DVB channels
Implements K=7, (171
8
,133
8
) Viterbi decoder for rates 1/2, 2/3, 3/4, 5/6 and 7/8
with a survivor depth of 96
Code rate and synchronization control programmable via I
2
C standard serial bus
Automatic rate selection and signal quality output (qval)
Full/empty flag generation of input FIFO for system monitoring of VDCLK/BITCLK
ratio
Simplified system design with internal PLL for the generation of output BITCLK
from the incoming VDCLK for all depuncturing modes
Available in a 128QFP package
Figure 1. Viterbi Decoder Block Diagram
MC92300
DTVVIT
RESET_N
VC0,VC1[2:0]
VDCLK
VFF
VEF
BITCLK
VO
SDA
DSA[6:0]
SCL
VLCK
VTSTI[1:0]
SR[2:0]
Ordering Information
Device
MC92300CG
Package
128QFP
SYMCLK
VC1[2:0]
VC2[2:0]
VDCLK
Synchronizer
FIFO
Depuncturing
Viterbi
Core
VFF
VEF
BIT-
CLK
VO
SYMCLK
VLCK
SR
QVAL
VTSTI[1:0]
I
2
C
Interface
RESET_N
2
APLL
SCL DSA SDA
7
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
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