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參數資料
| 型號： | MC92300CG |
| 廠商： | Motorola, Inc. |
| 英文描述： | VITERBI Decoder for Digital TV |
| 中文描述： | 維特比譯碼數字電視 |
| 文件頁數： | 2/4頁 |
| 文件大?。?/td> | 42K |
| 代理商： | MC92300CG |
2
Rev.1.3
MOTOROLA
MC92300
Product Description
The Viterbi Decoder contains
the Viterbi core logic,
which operates the K=7 convolutional code and generates
a lock indication after successful acquisition. The core
works with the main clock BITCLK, which provides the out-
put data VO (output of the Viterbi). This clock is generated
by the integrated bit clock generator circuit and is adjusted
according to the programmed depuncturing rate.
The input to the chip are 3 bit soft decision data VC0/1
from the QPSK demodulator together with the associated
demodulator clock VDCLK. Rate adjustment in accordance
with the several depuncturing rates is achieved with the in-
put FIFO. The data is read into the depuncturing logic with
the internally generated BITCLK.
Generator Polynomials
The Viterbi decoder is designed to decode bit streams
encoded using the DVB standard generator polynomials
(171
8
, 133
8
).
Punctured Codes
The Viterbi Decoder is able to decode a basic rate 1/2
convolutional code and the “standard” punctured codes for
a k=7 constraint length. The punctured codes are shown in
the table below. Specific bits of the original rate 1/2 code se-
quence are periodically deleted prior to transmission ac-
cording to the entries in the table, where a 0 means that the
bit is deleted and a 1 means that the bit is transmitted.
Synchronization
Prior to outputting valid data the Viterbi decoder block
must synchronize to the input data stream, i.e. remove any
phase ambiguity in the received symbols and determine the
punctured code rate transmitted
Table 1 Deletion Map For Punctured Rate 1/2 Codes
Coding
Rate
Puncture
Map
1/2
1
1
2/3
11
10
3/4
110
101
5/6
11010
10101
7/8
1111010
1000101
The Viterbi block employs a method known as Syndrom
Based Node Synchronization to achieve both I & Q symbol
and punctured rate synchronization.
The theory of the Syndrom Based Node Synchronization is
based on the observation that the product of the incoming
data and a syndrom is zero if there are no errors If errors are
present in the data, the probability of 0’s and 1’s in the prod-
uct increases.
The possible states that the synchronizer has to deal with
are a combination of the following factors:
1.The phasing of the received symbols.
I & Q input streams can either be processed as-is or
can be rotated 90
o
to account for constellation
rotation in the receiver.
2. Determination of the framing of the I and Q bit
streams so as to extract the correct symbol. There
are four possible ways to frame the two bit stream
and the synchronizer must determine the correct
one.
I
2
C Interface
The internal registers of the VITERBI are accessible
via the I
2
C interface. After reset, default values are prepro-
grammed, so that no more configuration is necessary.
APLL
In order to allow a simple system design, a Analogue
PLL is integrated for generation of the output Bit Clock. The
following output frequencies R
o
are generated for a given
DVB transponder Bandwidth TBW respectively for a given
input symbol rate R
s
.
TBW[MHz]
R
s
[MHz]
R
o
[MHz] for rates
1/2
2/3
3/4
5/6
7/8
36
33
30
27
26
38.3
28.3 37.7 42.4 47.2 49.5
20.5
20.5 27.3 30.7 34.2 35.9
R
s
/R
o
1
4/3
3/2
5/3
7/4
Application
The MC92300 is used in satellite receiver implementa-
tion for DVB.
Packaging
The MC92300 is available in a 128-pin Plastic Quad
Flat Pack (128QFP) package.
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