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參數資料
| 型號： | MCM101525B15 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 2M x 2 Bit Fast Static Random Access Memory with ECL I/O |
| 中文描述： | 200萬× 2位快速靜態隨機存取的ECL的I /內存? |
| 文件頁數： | 5/8頁 |
| 文件大?。?/td> | 454K |
| 代理商： | MCM101525B15 |
MCM101525
5
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
MCM101525–12
MCM101525–15
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH,
tWLSH
12
—
15
—
ns
3
Address Setup Time
1
—
1
—
ns
Address Valid to End of Write
9
—
10
—
ns
Write Pulse Width
8
—
9
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWHQX
tWHQV
tWHAX
tWLQL
8
—
9
—
ns
Data Hold Time
1
—
1
—
ns
Write High to Output Active
4
—
4
—
ns
4
Write High to Output Valid
—
13
—
16
ns
Write Recovery Time
1
—
1
—
ns
Write Low to Output Low
0
8
0
9
ns
NOTES:
1. A write occurs during the overlap of S low and W low.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQL
tWHQX
A (ADDRESS)
S (CHIP SELECT)
Q/Q (DATA OUT)
D (DATA IN)
tWLSH
W (WRITE ENABLE)
tWHQV
DATA VALID
ADDRESS VALID
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and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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