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參數資料
| 型號： | MCM20014IBMN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 1/3” Color VGA Digital Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數： | 12/54頁 |
| 文件大小： | 761K |
| 代理商： | MCM20014IBMN |
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MOTOROLA
MCM20014
12
The standby mode is activated by applying an active
high signal to the STBY pin (#27). The sensor can also
be put in the stand by mode via bit <0> on the Power
Configuration Register (OC
h
)
The user may also reduce power consumption in the ac-
tive processing mode by placing the MCM20014
’
s out-
puts in the tri-state mode. This action may be
accomplished by placing the TS pin in the active high
state. This action can also accomplished by setting the
dbt
bit on the
Power Configuration Register; Table 14
,
(0C
h
).
2.4.3 References CVREFP, CVREFM
The MCM20014 contains all internally generated refer-
ences and biases on-chip for system simplification. An
internally generated differential bandgap regulator de-
rives all the ADC and other analog signal processing re-
quired references. The user should connect 0.1
μ
F
capacitors to the CVREFP and CVREFM pins (#19 and
#18 respectively) to accurately hold the biases.
2.4.4 Internal Timing Control Register
The
Internal Timing Control Register; Table 28
allows
control over pulse widths of critical internal timing sig-
nals. The user must write an 00
h
into this address loca-
tion to assure proper operation of the MCM20014.
2.4.5 Internal Bias Current Control
The ASP chain has internally generated bias currents
that result in an operating power consumption of nearly
400mW. By attaching a resistor between pin 13, EX-
TRES; and ground, the user can reduce the power con-
sumption of the device. This feature is enabled by
writing a 1
b
to bit
res
of the
Power Configuration Regis-
ter
.
Figure 14
depicts the power savings that can be
achieved with an external resistor at a specific clock
rate. Additional power savings can be acheived at lower
clock rates.
Figure 14. External Resistor Effect on Power Consumption at 13.5Mhz MCLK
3.0 MCM20014 Waveform Diagrams
The following set of diagrams depict the input/output
waveform relationships for the pixel data.
3.1 CFCM Data Waveforms
The following set of waveforms depict the CFCM output
data stream from a complete frame down to individual
signal relationships.
Figure 15
depicts a complete frame
of a CFCM output data stream in default mode.
Figure
16
depicts the first row of data in the frame.
Figure 17
and
Figure 18
depict the same CFCM wave-
forms with the Internal Timing Control Register loaded
with an 00
h
.
10
20
30
40
50
60
200
300
400
500
600
100
External Resistor (k
)
A
)
Internal Resistor Power Consumption
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