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參數(shù)資料
| 型號(hào)： | MCM32257BZ25 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 256K x 32 Bit Fast Static RAM Module |
| 中文描述： | 1M X 8 MULTI DEVICE SRAM MODULE, 25 ns, ZMA64 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 158K |
| 代理商： | MCM32257BZ25 |
MCM32257B
6–7
MOTOROLA FAST SRAM
WRITE CYCLE 2
(E Controlled, See Notes 1 and 2)
MCM32257B–15
MCM32257B–20
MCM32257B–25
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVEL
tAVEH
tELEH
tELWH
tWLEH
tDVEH
tEHDX
tEHAX
15
—
20
—
25
—
ns
3
Address Setup Time
0
—
0
—
0
—
ns
Address Valid to End of Write
12
—
15
—
17
—
ns
Enable to End of Write
10
—
12
—
15
—
ns
4,5
Enable to End of Write
10
—
12
—
15
—
ns
Write Pulse Width
10
—
12
—
15
—
ns
Data Valid to End of Write
7
—
8
—
10
—
ns
Data Hold Time
0
—
0
—
0
—
ns
Write Recovery Time
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don’t care when W is low.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
DATA VALID
HIGH–Z
tAVAV
tAVEH
tAVEL
tELEH
tELWH
tEHAX
tWLEH
tDVEH
tEHDX
A (ADDRESS)
Ex (BYTE ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
Motorola Memory Prefix
Part Number
ORDERING INFORMATION
(Order by Full Part Number)
MCM
32257B
X
XX
Full Part Numbers — MCM32257BZ15
MCM32257BZ20
MCM32257BZ25
Package (Z = ZIP Module)
Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns)
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