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參數資料
| 型號： | MCM32515SG25 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 512K x 32 Bit Fast Static RAM Module |
| 中文描述： | 2M X 8 MULTI DEVICE SRAM MODULE, 25 ns, ZMA72 |
| 封裝： | SIMM-72 |
| 文件頁數： | 6/8頁 |
| 文件大小： | 79K |
| 代理商： | MCM32515SG25 |
MCM32515
6
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
MCM32515–20
MCM32515–25
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tWLWH,
tWLEH
20
—
25
—
ns
3
Address Setup Time
0
—
0
—
ns
Address Valid to End of Write
15
—
17
—
ns
Write Pulse Width
15
—
17
—
ns
Data Valid to End of Write
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
10
—
10
—
ns
Data Hold Time
0
—
0
—
ns
Write Low to Data High–Z
0
9
0
10
ns
4,5,6
Write High to Output Active
5
—
5
—
ns
4,5,6
Write Recovery Time
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don‘t care when W is low.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
DATA VALID
HIGH–Z
HIGH–Z
tAVAV
tAVWH
tWHAX
tWHDX
tWHQX
tWLWH
tAVWL
tDVWH
tWLQZ
A (ADDRESS)
Ex (BYTE ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
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