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參數資料
| 型號： | MCM6249WJ35R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 1M x4 Bit Static Random Access Memory |
| 中文描述： | 1M X 4 STANDARD SRAM, 35 ns, PDSO32 |
| 封裝： | 0.400 INCH, SOJ-32 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 116K |
| 代理商： | MCM6249WJ35R2 |
MCM6249
1
Motorola, Inc. 1995
1M x 4 Bit Static Random
Access Memory
The MCM6249 is a 4,194,304 bit static random access memory organized as
1,048,576 words of 4 bits, fabricated using high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6249 is equipped with chip enable (E) and output enable (G) pins,
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high impedance.
The MCM6249 is available in a 400 mil, 32–lead surface–mount SOJ package.
Single 5 V
±
10% Power Supply
Fast Access Time: 20/25/35 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
Power Operation: 190/175/160 mA Maximum, Active AC
BLOCK DIAGRAM
G
A18
A17
A16
A15
A14
A19
A3
A2
A1
A0
MEMORY MATRIX
1024 ROWS x
4096 COLUMNS
ROW
DECODER
INPUT
DATA
CONTROL
A11
A10
A9
A8
A7
A6
A5
A4
DQ0
DQ3
E
W
A13
A12
COLUMN I/O
COLUMN DECODER
DQ0
DQ3
Order this document
by MCM6249/D
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6249
A0 – A19
W
. . . . . . . . . . . . . . . . . . . .
G
. . . . . . . . . . . . . . . . . . .
E
. . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ3
. . . . . . . .
NC
. . . . . . . . . . . . . . . . .
VCC
. . . . . . . . . . . .
VSS
. . . . . . . . . . . . . . . . . . . . . . .
Address Inputs
Write Enable
Output Enable
Chip Enable
Data Input/Output
No Connection
+ 5 V Power Supply
. . . . . . . . . . . .
Ground
PIN NAMES
WJ PACKAGE
400 MIL SOJ
CASE 857A–02
32
31
30
29
28
27
26
25
24
23
22
21
2
3
1
5
6
4
7
9
10
8
12
13
11
14
20
15
16
19
18
17
A8
A9
A17
A6
E
A11
W
A13
A18
A10
VCC
VSS
A16
A14
A3
A15
DQ2
A2
G
DQ3
A4
A19
A5
A0
VCC
VSS
DQ0
DQ1
A7
A1
A12
NC
REV 4
5/95
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MCM6256AP12 | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:Dynamic RAM, Page Mode, 256K x 1, 16 Pin, Plastic, DIP |
| MCM6256BP-10 | 制造商:Motorola Inc 功能描述:PULLS |
| MCM6256BP12 | 制造商:Motorola Inc 功能描述:Dynamic RAM, Page Mode, 256K x 1, 16 Pin, Plastic, DIP |
| MCM6256BP-12 | 制造商:Motorola Inc 功能描述:PULLS |
| MCM6264BNJ35R2 | 制造商:Motorola Inc 功能描述:8K X 8 STANDARD SRAM, 35 ns, PDSO28 |
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