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參數資料
| 型號： | MCVVQ111AFB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 顯示驅動器 |
| 英文描述： | VirtuoVue Monochrome Video Display Driver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數： | 13/18頁 |
| 文件大小： | 175K |
| 代理商： | MCVVQ111AFB |
MOTOROLA
REV 0 Page 13
Jan. 2002
MCVVQ111AFB
FUNCTIONAL DESCRIPTION
(Refer to Figure 1)
The MCVVQ111AFB is designed to receive a standard monochrome video signal (525 or 625 lines) at Pin 5, and drive the
CyberDisplay320
LCD display panel. The IC contains the following sections:
PLL
- The PLL will normally lock to the horizontal frequency of the incoming video (via the sync separator) so as to
synchronize the timing generator with the video amplifiers. The component values shown at pin 7 are suitable for both 525/60 and
625/50 signals. The PLL output frequency is 384xFh, or 6.05MHz for a standard 525 line/60Hz signal (NTSC), and 6MHz for a
standard 625 line/50 Hz signal (PAL/SECAM). The timing generator provides all the timing signals to the LCD panel.
Pins 45 and 46 (HSync and VSync) can be configured as inputs or outputs, controlled by pin 47(VHIO Sel). When Pin 47
is low, pins 45 and 46 are outputs. HSync out is a square wave at the horizontal frequency as shown in Figure 4. VSync out is an
active high pulse as shown in Figure 5.
When pin 47 is high, pins 45 and 46 are inputs, require negative sync input pulses. This permits synchronizing the
MCVVQ111AFB to an external signal.
When there is no video present, the PLL will continue to provide horizontal and vertical timing signals to the timing
generator so as to keep the LCD display active. The PLL frequency will decrease slightly in the absence of video, but will lock up
once a valid video signal is applied.
Voltage Regulator
- The section will provide all the necessary regulated supply voltages to the LCD display panel from an
external 11V supply(VDDH).
Figure 6 shows the various voltages required by the
CyberDisplay320
LCD panel.
Video Processor
- The video input is a standard 1.0 volt p-p composite monochrome video signal, either 525 or 625 lines.
If only color composite video is available, it is recommended that the chroma frequencies be filtered out prior to this IC.
The DC Restore section provides black level clamping. For this portion to function correctly, the source impedance of the
video signal must be <500. The clamp timing is shown in Figure 4 .
The sync separator will separate the horizontal and vertical timing signals from the incoming video, and provide them to
the timing generator, and to the PLL. The remaining luma information passes to the two output video amplifiers, via the OSD
switch, and the video adjust block.
The Black Level Adjust (pin 30) is a DC input, with an input range of 2.0 to 3.0 volts, setting the black level at VIDH and
VIDL according to Figure 2. The black level does not change if the voltage at pin 30 is increased past 3.0 volts, and it is not
affected by the Gain adjust(Pin 8).
The Gain Adjust(pin 8) input is a DC input, with a range of 1.25 to +2.5 volts, resulting in a 7 dB change at VIDL and
VIDH, as shown in Figure 3 . The gain of Figure 3 is from the Video Input(Pin 5) to VIDL & VIDH, measured from black level to
white level, excluding sync. Since VIDL’s upper limit (and VIDH’s lower limit) are clamped at 5.5 volts, the gain curve is valid as
long as the signals are not clamped.
Timing Generator
- This section provides the horizontal and vertical scaling, and the eight timing signals required by the
CyberDisplay320
LCD display panel. All fields of the incoming interlaced signal are provided to the display panel sequentially.
This section is synchronized by signals from the sync separator and PLL. The HCK frequency is same as PLL output frequency
(6.05 MHz or 6.0 MHz).
The vertical scaling algorithm depends on the setting of the 525/625 pin (pin 10). When set low (for 525/60 signals) no
vertical scaling occurs. When set high (for 625/50 signals) lines are skipped according to the following algorithms:
Odd field, line number 22+(12N+6) and 22+(12N+12) where N=0,1,2,3.... were skipped, or, the first skipped line is line 28,
Even field, line number 334+(12N+3) and 334+(12N+9) where N=0,1,2,3.... were skipped, or, the first skipped line is line
337,
Horizontally, a small portion of the left and right edges of the video content line is expanded. Figure 7 indicates the
horizontal timing.
All timing values are multiples of the HCK period. The eight timing signals to the
CyberDisplay320
LCD display panel are
(refer Figures 8-10):
PDR (pin 13) - Power Down Reset is high for normal operation. It is set low when the MCVVQ111AFB is set to the Sleep
mode.
VCK (pin 15) - Vertical Clock. The active low output appears every other line, indicating the beginning of an even numbered
row. It is present for video lines 22 through 260 only.
VPL (pin 16) - Vertical Start Pulse. This active low output appears once per field at line 22, to indicate the start of a field.
HODL (pin 17) - This output changes polarity to satisfy the HODL inversion requirement of the
CyberDisplay320
LCD
display panel. The changes occur during the back porch time of video lines 22 through 261 of each field, with an addition
change at line 4 of either Field 1 or 2, depending on the initial lock-up condition.
HPL (pin 23) - Horizontal Start Pulse. This active output indicates the beginning of each line. It is present for video lines 22
through 261 only.
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