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參數資料
| 型號： | MF5CWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | MF5 Universal Monolithic Switched Capacitor Filter |
| 中文描述： | SWITCHED CAPACITOR FILTER, RESISTOR PROGRAMMABLE, UNIVERSAL, PDSO14 |
| 封裝： | SO-14 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 293K |
| 代理商： | MF5CWM |
Pin Description
LP(14), BP(1),
N/AP/HP(2):
The second order lowpass, bandpass,
and notch/allpass/highpass outputs. The
LP and BP outputs can typically sink 1 mA
and source 3 mA. The N/AP/HP output
can typically sink 1.5 mA and source 3
mA. Each output typically swings to within
1V of each supply.
The inverting input of the summing op
amp of the filter. This is a high impedance
input, but the non-inverting input is
internally tied to AGND, making INV1
behave like a summing junction (low
impedance current input).
S1 is a signal input pin used in the allpass
filter configurations (see modes 4 and 5).
The pin should be driven with a source
impedance of less than 1 k
X
. If S1 is not
driven with a signal it should be tied to
AGND (mid-supply).
This pin activates a switch that connects
one of the inputs of the filter’s second
summer to either AGND (SA tied to V
b
)
or to the lowpass (LP) output (SA tied to
V
a
). This offers the flexibility needed for
configuring the filter in its various modes
of operation.
This pin is used to set the internal clock to
center frequency ratio (f
CLK
/f
o
) of the
filter. By tying the pin to V
a
an f
CLK
/f
o
ratio of about 50:1 (typically 50.11
g
0.2%) is obtained. Tying the 50/100 pin to
either AGND or V
b
will set the f
CLK
/f
o
ratio to about 100:1 (typically 100.04
g
0.2%).
This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or biased
to mid-supply for single supply operation.
For a further discussion of mid-supply
biasing techniques see the Applications
Information (Section 3.2). For optimum
filter performance a ‘‘clean’’ ground must
be provided.
INV1(3):
S1(4):
SA(5):
50/100(9):
AGND(11):
V
a
(6), V
b
(10):
These are the positive and negative
supply pins. The MF5 will operate over a
total supply range of 8V to 14V.
Decoupling the supply pins with 0.1
m
F
capacitors is highly recommended.
This is the clock input for the filter. CMOS
or TTL logic level clocks can be
accomodated by setting the L. Sh pin to
the levels described in the L. Sh pin
description. For optimum filter
performance a 50% duty cycle clock is
recommended for clock frequencies
greater than 200 kHz. This gives each op
amp the maximum amount of time to
settle to a new sampled input.
This pin allows the MF5 to accommodate
either CMOS or TTL logic level clocks. For
dual supply operation (i.e.,
g
5V), a CMOS
or TTL logic level clock can be accepted if
the L. Sh pin is tied to mid-supply (AGND),
which should be the system ground.
For single supply operation the L. Sh pin
should be tied to mid-supply (AGND) for a
CMOS logic level clock. The mid-supply
bias should be a very low impedance
node. See Applications Information for
biasing techniques. For a TTL logic level
clock the L. Sh pin should be tied to V
b
which should be the system ground.
This is the inverting input of the
uncommitted op amp. This is a very high
impedance input, but the non-inverting
input is internally tied to AGND, making
INV2 behave like a summing junction
(low-impedance current input).
This is the output of the uncommitted op
amp. It will typically sink 1.5 mA and
source 3.0 mA. It will typically swing to
within 1V of each supply.
CLK(8):
L. Sh(7):
INV2(12):
Vo2(13):
Typical Performance Characteristics
Deviation ofF
CLK
F
o
vs Nominal Q
Deviation ofF
CLK
F
o
vs Nominal Q
OPAMP Output Voltage
Swing vs Temperature
TL/H/5066–3
4
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