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參數資料
| 型號： | MH16D72AKLB-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:79; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:20-35 RoHS Compliant: No |
| 中文描述： | 1,207.959,552位（16,777,216 - Word的72位），雙數據速率同步DRAM模塊 |
| 文件頁數： | 17/39頁 |
| 文件大小： | 348K |
| 代理商： | MH16D72AKLB-10 |
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MITSUBISHI LSIs
MITSUBISHI ELECTRIC
MH16D72AKLB-10,75
1,207.959,552-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0397-1.1
24.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
17
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70 , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
C
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70 C
355
427
1948
2110
1723
1885
1768
1930
868
985
688
760
688
760
508
580
1318
1435
1273
1390
-10
-75
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
mA
mA
mA
SELF REFRESH CURRENT: CKE 0.2V
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; CL = 2.5; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One
bank active; Address and control inputs changing once per clock
cycle; CL = 2.5; t CK = t CK MIN; IOUT = 0 mA
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
DQ,DM and DQS inputs changing twice per clock cycle; address and
other control inputs changing once per clock cycle
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
IDD2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
mA
OPERATING CURRENT: One Bank; Active-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0
mA;Address and control inputs changing once per clock cycle
OPERATING CURRENT: One Bank; Active-Precharge;
t RC = t RC MIN; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle; address and control inputs changing once per
clock cycle
Parameter/Test Conditions
IDD4R
IDD3N
mA
mA
mA
mA
mA
mA
IDD6
IDD5
IDD4W
IDD3P
IDD2N
IDD1
IDD0
Notes
Unit
Limits(max)
Symbol
Symbol
Parameter/Test Conditions
Limits
Min.
Max.
Unit
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
High-Level Input Voltage (AC)
Low-Level Input Voltage (AC)
Input Differential Voltage, CLK and /CLK
Input Crossing Point Voltage, CLK and /CLK
Vref + 0.35
Vref - 0.35
V
V
V
V
μA
0.7
0.5*V
DD
Q-0.2
V
DD
Q + 0.6
IOZ
I
i
Off-state Output Current /Q floating Vo=0~V
DD
Q
Input Current / VIN=0 ~ VddQ
μA
-5
-2
5
2
0.5*V
DD
Q+0.2
Notes
7
8
9
O
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