- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371104 > MH16S64APFC-7L (Mitsubishi Electric Corporation) 1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM PDF資料下載
參數(shù)資料
| 型號： | MH16S64APFC-7L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 1073741824位（16,777,216 -文字，64位）SynchronousDRAM |
| 文件頁數(shù)： | 19/52頁 |
| 文件大小： | 1042K |
| 代理商： | MH16S64APFC-7L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 52 )
19
MITSUBISHI
ELECTRIC
4. Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0127-0.0
Dual Bank Interleaving WRITE (BL=4)
CK
Command
A10
DQ
ACT
Xa
Xa
0
Write
Y
0
0
Write
Y
0
1
Da0
Da1
Da2
Da3
ACT
Xb
Xb
1
PRE
0
0
tRCD
Burst Length
Db0
Db1
Db2
Db3
tRCD
tWR
CK
Command
A10
DQ
ACT
Xa
Xa
0
Write
Y
1
0
Da0
Da1
Da2
Da3
ACT
Xa
Xa
0
Internal precharge begins
tRCD
tRP
tWR
WRITE with Auto-Precharge (BL=4)
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the
Burst Length is BL. The start address is specified by A9-0, and the address sequence of burst
data is defined by the Burst Type. A WRITE command may be applied to any active bank, so
the row precharge time(tRP) can be hidden behind continuous input data (in case of BL=8) by
interleaving the dual banks. From the last input data to the PRE command, the write recovery
time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA)
is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the
internal precharge is complete. The internal precharge begins at tWR after the last input data
cycle. The next ACT command can be issued after tRP from the internal precharge timing.
A0-9,11
BA0,1
A0-9,11
BA0,1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH16S64APFC-8 | 1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM |
| MH16S64APFC-8L | 1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM |
| MH16S64APHB-6 | 1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)Synchronous DRAM |
| MH16S64APHB-7 | 1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)Synchronous DRAM |
| MH16S64APHB-8 | 1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH16S64APFC-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM |
| MH16S64APFC-8L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)SynchronousDRAM |
| MH16S64APHB-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)Synchronous DRAM |
| MH16S64APHB-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)Synchronous DRAM |
| MH16S64APHB-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,073,741,824-BIT (16,777,216 - WORD BY 64-BIT)Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。