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參數(shù)資料
| 型號： | MH16S64DAMD-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 1073741824-BIT (16777216 - WORD BY 64-BIT)Synchronous DRAM |
| 中文描述： | 1073741824位（16777216 -文字，64位）同步DRAM |
| 文件頁數(shù)： | 4/52頁 |
| 文件大小： | 1042K |
| 代理商： | MH16S64DAMD-6 |
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MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 4
MITSUBISHI
ELECTRIC
4. Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0127-0.0
Serial Presence Detect Table I
Byte
0
1
2
3
4
5
6
7
8
9
Function described
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A9
1BANK
x64
0
LVTTL
8ns
10ns
12ns
6ns
8ns
8ns
SPD DATA(hex)
80
08
04
0C
0A
01
40
00
01
80
A0
C0
60
80
80
00
80
04
00
01
0F
04
06
01
01
00
06
D0
E0
F0
70
80
90
00
00
00
00
00
00
18
1E
1E
10
14
18
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
-8
-10
-12
-8
-10
-12
10
SDRAM Access from Clock
tAC for CL=3
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Non-PARITY
self refresh(15.625uS)
x4
N/A
1
1/2/4/8
4bank
CL=2/3
0
0
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
non-buffered,non-registered
Precharge All,Auto precharge
13ns
14ns
15ns
7ns
8ns
9ns
N/A
N/A
N/A
N/A
N/A
N/A
24ns
30ns
30ns
16ns
20ns
24ns
-8
-10
-12
-8
-10
-12
-8
-10
-12
-8
-10
-12
-8
-10
-12
-8
-10
-12
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
Cycle time for CL=
26
SDRAM Access form Clock(3rd highest CAS latency)
tAC for CL=
27
Precharge to Active Minimum
28
Row Active to Row Active Min.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH16S64DAMD-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1073741824-BIT (16777216 - WORD BY 64-BIT)Synchronous DRAM |
| MH16S64DAMD-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1073741824-BIT (16777216 - WORD BY 64-BIT)Synchronous DRAM |
| MH16S64FFB-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM |
| MH16S64FFB-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM |
| MH16S64PFC-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM |
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