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參數資料
| 型號： | MH16S72AMA-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:3; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:12-3 RoHS Compliant: No |
| 中文描述： | 1207959552位（16777216 - Word的72位）SynchronousDRAM |
| 文件頁數： | 17/52頁 |
| 文件大小： | 1045K |
| 代理商： | MH16S72AMA-8 |
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MH16S72AMA -8,-10,-12
1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM
MITSUBISHI LSIs
( / 52 )
17
MITSUBISHI
ELECTRIC
5. Mar.1997
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0128-0.0
Bank Activation and Precharge All (BL=4, CL=3)
CK
Command
A0-9,11
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
Precharge all
tRAS
tRP
OPERATION DESCRIPTION
BANK ACTIVATE
The SDRAM has two independent banks. Each bank is activated by the ACT command with
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum
activation interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output date is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when
the Burst Length is BL. The start address is specified by A9-0, and the address sequence of
burst data is defined by the Burst Type. A READ command may be applied to any active bank,
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)
by interleaving the dual banks. When A10 is high at a READ command, the
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge start
timing depends on /CAD Latency. The next ACT command can be issued after tRP from the
internal precharge timing.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MH16S72APHB-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM |
| MH16S72APHB-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM |
| MH16S72APHB-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM |
| MH16S72AVJB-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM |
| MH16S72BAMD-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1207959552-BIT (16777216 - WORD BY 72-BIT)SynchronousDRAM |
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