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參數資料
| 型號： | Q67060-S6112-A2 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | High Speed CMOS Logic Dual 4-Input NOR Gates 14-SO -55 to 125 |
| 中文描述： | 智能阻抗高側電源開關一個頻道：20mз |
| 文件頁數： | 3/11頁 |
| 文件大小： | 216K |
| 代理商： | Q67060-S6112-A2 |
BTS 441 T
Infineon Technologies AG
3
2003-Oct-01
Maximum Ratings
at T
j
= 25 °C unless otherwise specified
Parameter
Supply voltage (overvoltage protection see page 4)
Supply voltage for full short circuit protection
T
j Start
=-40 ...+150°C
Load dump protection
1)
V
LoadDump
=
V
A
+
V
s
,
V
A
= 13.5 V
R
I
2)
= 2
,
R
L
= 0,5
,
t
d
= 200 ms, IN= low or high
Load current (Short-circuit current, see page 5)
Operating temperature range
Storage temperature range
Power dissipation (DC) ; TC
≤
25°C
Maximal switchable inductance, single pulse
V
bb
=
12V,
T
j,start
=
150°C,
T
C
=
150°C const.
(see diagram, p.8)
I
L(ISO)
=
21
A, RL= 0
:
E
4
)AS
=0.7J:
Electrostatic discharge capability (ESD)
(Human Body Model)
Out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and
ESD assn. std. S5.1-1993; R=1.5k
; C=100pF
Input voltage (DC)
Current through input pin (DC)
see internal circuit diagrams page 7
Symbol
V
bb
V
bb
Values
Unit
43
34
V
V
V
Load dump3)
60
V
I
L
T
j
T
stg
self-limited
-40 ...+150
-55 ...+150
A
°C
P
tot
Z
L
V
ESD
125
W
2.1
1.0
8.0
mH
kV
IN:
V
IN
I
IN
-10 ... +16
V
±
2.0
mA
Thermal resistance
R
thJC
R
thJA
chip - case:
junction - ambient (free air):
SMD version, device on pcb
5)
:
≤
1
≤
75
≤
33
K/W
1)
Supply voltages higher than V
bb(AZ)
require an external current limit for the GND pin, e.g. with a 150
resistor in the GND connection. A resistor for the protection of the input is integrated.
2)
R
I
= internal resistance of the load dump test pulse generator
3)
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
4)
E
AS
is the maximum inductive switch off energy
5)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70
μ
m thick) copper area for Vbb
connection. PCB is vertical without blown air.
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