- 您現在的位置：買賣IC網 > PDF目錄361235 > Q67100-Q543 (SIEMENS AG) 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM PDF資料下載
參數資料
| 型號： | Q67100-Q543 |
| 廠商： | SIEMENS AG |
| 英文描述： | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| 中文描述： | 256畝× 4位動態隨機存儲器的低功耗256畝× 4位動態隨機存儲器 |
| 文件頁數： | 9/53頁 |
| 文件大小： | 418K |
| 代理商： | Q67100-Q543 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
9
12.99
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Notes
1.
V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode
cycle device is clock suspend mode.
Operation
Device
State
Idle
3
Active
3
Active
3
CKE
n-1
CKE
n
CS
RAS
CAS
WE
DQM A0-9,
A11
A10
BA0
BA1
Row Activate (ACT)
H
X
L
L
H
H
X
V
V
V
Read (READ)
H
X
L
H
L
H
X
V
L
V
Read w/ Autoprecharge
(READA)
H
X
L
H
L
H
X
V
H
V
Write (WRITE)
Active
3
Active
3
H
X
L
H
L
L
X
V
L
V
Write w/ Autoprecharge
(WRITEA)
H
X
L
H
L
L
X
V
H
V
Row Precharge (PRE)
Any
H
X
L
L
H
L
X
X
L
V
Precharge All (PREA)
Any
H
X
L
L
H
L
X
X
H
X
Mode Register Set (MRS)
Idle
H
X
L
L
L
L
X
V
V
V
No Operation (NOP)
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect (INHBT)
Any
H
X
H
X
X
X
X
X
X
X
Auto Refresh (REFA)
Idle
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry (REFS-EN) Idle
H
L
L
L
L
H
X
X
X
X
Self Refresh Exit (REFS-EX)
Idle
(Self
Refr.)
L
H
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Entry (PDN-EN) Idle
Active
5
H
L
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Exit (PDN-EX)
Any
(Power
Down)
L
H
H
X
X
X
X
X
X
X
L
H
H
L
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Write/Output Disable
Active
H
X
X
X
X
X
H
X
X
X
相關PDF資料 |
PDF描述 |
|---|---|
| Q67100-Q607 | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| Q67100-Q608 | 256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| Q67100-Q651 | 1M x 36-Bit Dynamic RAM Module (2M x 18-Bit Dynamic RAM Module) |
| Q67100-Q727 | 256k x 16-Bit Dynamic RAM |
| Q67100-Q741 | 1M x 36-Bit Dynamic RAM Module (2M x 18-Bit Dynamic RAM Module) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| Q67100-Q607 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| Q67100-Q608 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM |
| Q67100-Q651 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 36-Bit Dynamic RAM Module (2M x 18-Bit Dynamic RAM Module) |
| Q67100-Q727 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256k x 16-Bit Dynamic RAM |
| Q67100-Q741 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 36-Bit Dynamic RAM Module (2M x 18-Bit Dynamic RAM Module) |
發布緊急采購，3分鐘左右您將得到回復。