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參數資料
| 型號： | Q67100-Q741 |
| 廠商： | SIEMENS AG |
| 英文描述： | 1M x 36-Bit Dynamic RAM Module (2M x 18-Bit Dynamic RAM Module) |
| 中文描述： | 100萬× 36位動態RAM模塊（2米× 18位動態隨機存儲器模塊） |
| 文件頁數： | 16/53頁 |
| 文件大小： | 418K |
| 代理商： | Q67100-Q741 |
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HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
16
12.99
Operating Currents
T
A
= 0 to 70
°
C,
V
DD
= 3.3 V
±
0.3 V
(Recommended Operating Conditions unless otherwise noted)
Notes
3. These parameters depend on the cycle rate and these values are measured at 133 MHz for -7.5,
and at 100 MHz for -8 components. Input signals are changed once during
t
CK
, excepts for
I
CC6
and for standby currents when
t
CK
= infinity.
4. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 is assumed and the
V
DDQ
current is excluded.
Parameter & Test Condition
Symb. -7.5 -8
Unit
Note
max.
Operating Current
t
RC
=
t
RC(MIN.)
,
t
CK
=
t
CK(MIN.)
Outputs open, Burst Length = 4, CL=3
All banks operated in random access,
all banks operated in ping-pong
manner to maximize gapless data
access
–
I
CC1
x4
x8
x16
110
120
140
100
110
130
mA
mA
mA
3
Precharge Standby Current
in Power Down Mode
CS =
V
IH (MIN.)
, CKE
≤
V
IL(MAX.)
Precharge Standby Current
in Non-Power Down Mode
CS =
V
IH (MIN.)
, CKE
≥
V
IH(MIN.)
No Operating Current
t
CK
= min., CS =
V
IH (MIN.)
,
active state (max. 4 banks)
t
CK
= min
t
CK
= infinity
I
CC2P
I
CC2PS
2
2
mA
3
1
1
mA
3
t
CK
= min
t
CK
= infinity
I
CC2N
I
CC2NS
40
35
mA
3
5
5
mA
3
CKE
≥
V
IH(MIN.)
CKE
≤
V
IL(MAX.)
I
CC3N
I
CC3P
50
45
mA
3
8
8
mA
3
Burst Operating Current
t
CK
= min
Read command cycling
–
I
CC4
x4
x8
x16
70
80
110
60
70
100
mA
mA
mA
3, 4
Auto Refresh Current
t
CK
= min
Auto Refresh command cycling
–
I
CC5
140 130 mA
3
Self Refresh Current
Self Refresh Mode
CKE = 0.2 V
standard
version
I
CC6
1
1
mA
3
L-version
400 400
μ
A
3
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