- 您現在的位置：買賣IC網 > PDF目錄371046 > MC68C912B32CFU8 (MOTOROLA INC) 16-Bit Microcontroller PDF資料下載
參數資料
| 型號： | MC68C912B32CFU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 116/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68C912B32CFU8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁當前第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
MOTOROLA
116
MC68HC912B32
MC68HC912B32TS/D
commands, but can steal cycles from the CPU when necessary. Other BDM commands are firmware
based, and require the CPU to be in active background mode for execution. While BDM is active, the
CPU executes a firmware program located in a small on-chip ROM that is available in the standard 64-
Kbyte memory map only while BDM is active.
The BDM control logic communicates with an external host development system serially, via the BKGD
pin. This single-wire approach minimizes the number of pins needed for development support.
16.2.1 Enabling BDM Firmware Commands
BDM is available in all operating modes, but must be made active before firmware commands can be
executed. BDM is enabled by setting the ENBDM bit in the BDM STATUS register via the single wire
interface (using a hardware command; WRITE_BD_BYTE at $FF01). BDM must then be activated to
map BDM registers and ROM to addresses $FF00 to $FFFF and to put the MCU in active background
mode.
After the firmware is enabled, BDM can be activated by the hardware BACKGROUND command, by
the BDM tagging mechanism, or by the CPU BGND instruction. An attempt to activate BDM before firm-
ware has been enabled causes the MCU to resume normal instruction execution after a brief delay.
BDM becomes active at the next instruction boundary following execution of the BDM BACKGROUND
command, but tags activate BDM before a tagged instruction is executed.
In special single-chip mode, background operation is enabled and active immediately out of reset. This
active case replaces the M68HC11 boot function, and allows programming a system with blank mem-
ory.
While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06. The
BDM control logic uses these registers which can be read anytime by BDM logic, not user programs.
Refer to
16.2.4 BDM Registers
for detailed descriptions.
Some on-chip peripherals have a BDM control bit which allows suspending the peripheral function dur-
ing BDM. For example, if the timer control is enabled, the timer counter is stopped while in BDM. Once
normal program flow is continued, the timer counter is re-enabled to simulate real-time operations.
16.2.2 BDM Serial Interface
The BDM serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is trans-
mitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU.
Data is transferred MSB first at 16 E-clock cycles per bit (nominal speed). The interface times out if 256
E-clock cycles occur between falling edges from the host. The hardware clears the command register
when a time-out occurs.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to MCU clocks but asynchronous
to the external host. The internal clock signal is shown for reference in counting cycles.
Figure 27
shows an external host transmitting a logic one or zero to the BKGD pin of a target
MC68HC912B32 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the
host-generated falling edge to where the target perceives the beginning of the bit time. Nine target E
cycles later, the target senses the bit level on the BKGD pin. Typically the host actively drives the pseu-
do-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Since the target
does not drive the BKGD pin during this period, there is no need to treat the line as an open-drain signal
during host-to-target transmissions.
相關PDF資料 |
PDF描述 |
|---|---|
| MC68CK338 | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| MC68EC060 | 32-Bit Microprocessors.(32位微處理器) |
| MC68EN360RC25V | QUad Integrated Communications Controller Users Manual |
| MC68EN360CFE25 | QUad Integrated Communications Controller Users Manual |
| MC68EN360FE25 | AC 4C 4#12 PIN PLUG 023 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68C912B32FU8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-Bit Microcontroller |
| MC68CK16Z1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
| MC68CK16Z1CAG16 | 功能描述:16位微控制器 - MCU 16BIT 1KRAM 32KHZ CRYSTAL RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| MC68CK16Z1CAG16 | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
| MC68CK16Z1CFC16 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC16Z Series |
發布緊急采購，3分鐘左右您將得到回復。