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參數資料
| 型號： | MC68EC060 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessors.(32位微處理器) |
| 中文描述： | 32位微處理器。（32位微處理器） |
| 文件頁數： | 7/10頁 |
| 文件大小： | 68K |
| 代理商： | MC68EC060 |
MOTOROLA
MC68060 PRODUCT INFORMATION
7
MEMORY MANAGEMENT UNITS
(MC68060 AND MC68LC060 ONLY)
The MC68060 contains independent instruction and data MMUs. Each MMU contains a cache memory called
the address translation cache (ATC). The full addressing range of the MC68060 is four Gbytes (4,294,967,296
bytes). Even though most MC68060 systems implement a much smaller physical memory, by using virtual
memory techniques, the system can appear to have a full four Gbytes of physical memory available to each
user program. Each MMU fully supports demand-paged virtual-memory operating systems with either 4- or 8-
Kbyte page sizes. Each MMU protects supervisor areas from accesses by user programs and provides write
protection on a page-by-page basis. For maximum efficiency, each MMU operates in parallel with other
processor activities. The MMUs can be disabled for emulator and debugging support.
The 64-entry, four-way, set-associative ATCs store recently used logical-to-physical address translation
information as page descriptors for instruction and data accesses. Each MMU initiates address translation by
searching for a descriptor containing the address translation information in the ATC. If the descriptor does not
reside in the ATC, the MMU performs external bus cycles through the bus controller to search the translation
tables in physical memory. After being located, the page descriptor is loaded into the ATC, and the address is
correctly translated for the access.
INSTRUCTION AND DATA CACHES
Studies have shown that typical programs spend much of their execution time in a few main routines or tight
loops. Earlier members of the M68000 family took advantage of this locality-of-reference phenomenon to
varying degrees. The MC68060 takes further advantage of cache technology with its two, independent, on-
chip physical caches, one for instructions and one for data. The caches reduce the processor's external bus
activity and increase CPU throughput by lowering the effective memory access time. For a typical system
design, the large caches of the MC68060 yield a very high hit rate, providing a substantial increase in system
performance.
The autonomous nature of the caches allows instruction-stream fetches, data-stream fetches, and external
accesses to occur simultaneously with instruction execution. For example, if the MC68060 requires both an
instruction access and an external peripheral access and if the instruction is resident in the on-chip cache, the
peripheral access proceeds unimpeded rather than being queued behind the instruction fetch. If a data
operand is also required and it is resident in the data cache, it can be accessed without hindering either the
instruction access or the external peripheral access. The parallelism inherent in the MC68060 also allows
multiple instructions that do not require any external accesses to execute concurrently while the processor is
performing an external access for a previous instruction.
Each MC68060 cache is eight Kbytes and is accessed by physical addresses. The data cache can be
configured as write-through or deferred copyback on a page basis. This choice allows for optimizing the
system design for high performance when deferred copyback is used.
Cachability of data in each memory page is controlled by two bits in the page descriptor. Cachable pages can
be either write-through or copyback, with no write-allocate for misses to write-through pages.
The MC68060 implements a four-entry write buffer that maximizes system performance by decoupling the
integer pipeline from the external system bus. When needed, the write buffer allows the pipeline to generate
writes every clock cycle, even if the system bus runs at a slower speed than the processor.
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