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| 型號(hào)： | MC68HC05B8 |
| 廠(chǎng)商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁(yè)數(shù)： | 108/298頁(yè) |
| 文件大小： | 3532K |
| 代理商： | MC68HC05B8 |
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MOTOROLA
9-4
MC68HC05B6
Rev. 4
RESETS AND INTERRUPTS
9
cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In
addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this
bit clears the counter to its initial value and prevents a watchdog timeout.
WDOG — Watchdog enable/disable
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set)
–
Watchdog enabled and counter cleared.
0 (clear) –
The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
The divide-by-8 watchdog counter will generate a main reset of the chip when it reaches its final
state; seven clocks are necessary to bring the watchdog counter from its clear state to its final
state. This reset appears after time t
DOG
since the last clear or since the enable of the watchdog
counter system. The watchdog counter, therefore, has to be cleared periodically, by software, with
a period less than t
DOG
.
The reset generated by the watchdog system is apparent at the RESET pin (see Figure 9-2). The
RESET pin level is re-entered in the control logic, and when it has been maintained at level ‘zero’
for a minimum of t
DOGL
, the RESET pin is released.
9.1.4.1
COP watchdog during STOP mode
The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is
executed while the watchdog system is enabled, then a watchdog reset will occur as if there were
a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will
not be affected, thus there will be no t
PORL
cycles start-up delay. On start-up, the watchdog will be
configured according to the user specified mask option.
9.1.4.2
COP watchdog during WAIT mode
The state of the watchdog during WAIT mode is selected via a mask option (see Section 1.2) to
be one of the options below:
Watchdog enabled — the watchdog counter will continue to operate during WAIT mode and a reset
will occur after time t
DOG
.
Watchdog disabled — on entering WAIT mode, the watchdog counter system is reset and
disabled. On exiting WAIT mode the counter resumes normal operation.
TPG
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05BD3 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
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| MC68HC05C0CP | 制造商:Motorola Inc 功能描述: |
| MC68HC05C12 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
| MC68HC05C12B | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS |
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