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參數(shù)資料
| 型號(hào)： | MC68HC11E20VFU2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:5.1"; External Width:5.1"; External Depth:3" |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 137/268頁 |
| 文件大小： | 3696K |
| 代理商： | MC68HC11E20VFU2 |
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Serial Peripheral Interface (SPI)
SPI System Errors
M68HC11E Family — Rev. 5
Data Sheet
MOTOROLA
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
137
between successive SPI characters. In cases where there is only one SPI slave
MCU, its SS line can be tied to V
SS
as long as only CPHA = 1 clock mode is used.
8.6 SPI System Errors
Two system errors can be detected by the SPI system. The first type of error arises
in a multiple-master system when more than one SPI device simultaneously tries
to be a master. This error is called a mode fault. The second type of error, write
collision, indicates that an attempt was made to write data to the SPDR while a
transfer was in progress.
When the SPI system is configured as a master and the SS input line goes to active
low, a mode fault error has occurred — usually because two devices have
attempted to act as master at the same time. In cases where more than one device
is concurrently configured as a master, there is a chance of contention between
two pin drivers. For push-pull CMOS drivers, this contention can cause permanent
damage. The mode fault mechanism attempts to protect the device by disabling the
drivers. The MSTR control bit in the SPCR and all four DDRD control bits
associated with the SPI are cleared and an interrupt is generated subject to
masking by the SPIE control bit and the I bit in the CCR.
Other precautions may need to be taken to prevent driver damage. If two devices
are made masters at the same time, mode fault does not help protect either one
unless one of them selects the other as slave. The amount of damage possible
depends on the length of time both devices attempt to act as master.
A write collision error occurs if the SPDR is written while a transfer is in progress.
Because the SPDR is not double buffered in the transmit direction, writes to SPDR
cause data to be written directly into the SPI shift register. Because this write
corrupts any transfer in progress, a write collision error is generated. The transfer
continues undisturbed, and the write data that caused the error is not written to the
shifter.
A write collision is normally a slave error because a slave has no control over when
a master initiates a transfer. A master knows when a transfer is in progress, so
there is no reason for a master to generate a write-collision error, although the SPI
logic can detect write collisions in both master and slave devices.
The SPI configuration determines the characteristics of a transfer in progress. For
a master, a transfer begins when data is written to SPDR and ends when SPIF is
set. For a slave with CPHA equal to 0, a transfer starts when SS goes low and ends
when SS returns high. In this case, SPIF is set at the middle of the eighth SCK
cycle when data is transferred from the shifter to the parallel data register, but the
transfer is still in progress until SS goes high. For a slave with CPHA equal to 1,
transfer begins when the SCK line goes to its active level, which is the edge at the
beginning of the first SCK cycle. The transfer ends in a slave in which CPHA
equals 1 when SPIF is set.
F
Freescale Semiconductor, Inc.
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.
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