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參數資料
| 型號： | MC68HC16Y1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Modular Microcontroller(16位模塊化微控制器) |
| 中文描述： | 16位微控制器模塊（16位模塊化微控制器） |
| 文件頁數： | 114/122頁 |
| 文件大小： | 749K |
| 代理商： | MC68HC16Y1 |
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MOTOROLA
114
MC68HC16Y1
MC68HC16Y1TS/D
PDS — Standby Power Status Bit
0 = Loss of standby power.
1 = No loss of standby power
The RAM array can be powered by a standby power source (V
STBY
) while V
DD
to the microcontroller is
turned off. PDS indicates when V
STBY
has fallen below a reference level for a specified period of time.
To detect power loss, software must first set PDS, then monitor its state during normal operation and
following reset.
RASP[1:0] — RAM Array Space Field
o = TPURAM array is placed in unrestricted space
1 = TPURAM array is placed in supervisor space.
This bit limits access to the SRAM array in microcontrollers that support separate user and supervisor
operating modes. Because the CPU16 in the MC68HC16Y1 operates in supervisor mode only, RASP
has no effect.
TRAMTST
— RAM Test Register
TRAMTST is used for factory test of the TPURAM module.
$YFFB02
TRAMBAR is used to specify an array base address in the system memory map. This prevents acci-
dental remapping of the array. TRAMBAR can be written only once after reset.
TRAMBAR[15:3] — RAM Array Base Address Field
This field specifies bits [23:11] of the array base address. The array must be enabled in order to be ac-
cessed. Since the states of ADDR[23:20] follow the state of ADDR19 in the MC68HC16Y1, addresses
in the range $080000 to $F7FFFF cannot be accessed.
RAMDS — RAM Array Disable Status Bit
0 = RAM array is enabled
1 = RAM array is disabled
RAMDS indicates whether the array is active or disabled. The array is disabled after reset. Writing a
valid base address into RAMBAR automatically clears RAMDS and enables the array.
8.3 TPURAM Operation
There are six TPURAM operating modes, as follows.
The RAM module is in normal mode when powered by V
DD
. The array can be accessed by byte, word,
or long word. A byte or aligned word (high-order byte is at an even address) access only takes one bus
cycle or two system clocks. A long word or misaligned word access requires two bus cycles.
Standby mode is intended to preserve RAM contents when V
DD
is removed. SRAM contents are main-
tained by V
STBY
. Circuitry within the SRAM module switches to the higher of V
DD
or V
STBY
with no loss
of data. When SRAM is powered by V
STBY
, access to the array is not guaranteed.
Reset mode allows the CPU to complete the current bus cycle before resetting. When a synchronous
reset occurs while a byte or word SRAM access is in progress, the access will be completed. If reset
occurs during the first word access of a long-word operation, only the first word access will be complet-
ed. If reset occurs during the second word access of a long word operation, the entire access will be
completed. Data being read from or written to the RAM may be corrupted by asynchronous reset.
TRAMBAR
— RAM Base Address and Status Register
$YFFB04
16
3
0
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
NOT
USED
RAMDS
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
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| MC68HC16Z1CAG | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC16Z1CAG16 | 功能描述:16位微控制器 - MCU 16 BIT MCU 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
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| MC68HC16Z1CAG20 | 功能描述:16位微控制器 - MCU 16 BIT MCU 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| MC68HC16Z1CAG20 | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
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