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參數資料
| 型號： | MC74HC251D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Input Data Selector/Multiplexer with 3-State Outputs |
| 中文描述： | HC/UH SERIES, 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-16 |
| 文件頁數： | 3/7頁 |
| 文件大小： | 213K |
| 代理商： | MC74HC251D |
MC54/74HC251
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1, 2 and 5)
4.5
37
56
6.0
35
46
53
tPLZ,
Maximum Propagation Delay, Output Enable to Output Y
2.0
195
245
43
295
ns
tPZH
(Figures 4 and 6)
4.5
29
44
6.0
37
36
56
tPZL,
Maximum Propagation Delay, Output Enable to Output Y
2.0
6.0
150
26
190
47
225
38
ns
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
75
15
33
110
22
ns
95
19
(Output in High–Impedance
State)
NOTES:
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
36
pF
PIN DESCRIPTIONS
INPUTS
D0, D1,
…
, D7 (Pins 4, 3, 2, 1, 15, 14, 13, 12)
Data inputs. Data on one of these eight binary inputs may
be selected to appear on the output.
CONTROL INPUTS
A0, A1, A2 (Pins 11, 10, 9)
Address inputs. The data on these pins are the binary ad-
dress of the selected input (see the Function Table).
Output Enable (Pin 7)
Output Enable. This input pin must be at a low level for the
selected data to appear at the outputs. If the Output Enable
pin is high, both the Y and Y outputs are taken to the high–
impedance state.
OUTPUTS
Y, Y (Pins 5, 6)
Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y output) forms.
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