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參數資料
| 型號： | MC74HC646 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal 3-State Bus Transceivers and D Flip-Flops |
| 中文描述： | 八路三態總線收發器和D觸發器 |
| 文件頁數： | 2/14頁 |
| 文件大小： | 328K |
| 代理商： | MC74HC646 |
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
Power Dissipation in Still Air,Plastic or Ceramic DIP
750
mW
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: –10 mW/ C from 65 to 125 C
Ceramic DIP: –10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
(Ceramic DIP)
300
Vin, Vout
TA
tr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
2.0
0
6.0
VCC
+ 125
V
V
Operating Temperature, All Package Types
– 55
C
Input Rise and Fall Time
0
0
1000
400
ns
VCC = 2.0 V
Symbol
Parameter
Test Conditions
V
– 55 to
25 C
85 C
1.5
4.2
4.2
125 C
1.5
4.2
VIH
Minimum High–Level Input
Vout = 0.1 V or VCC – 0.1 V
2.0
6.0
1.5
Unit
VIL
Maximum Low–Level Input
Vout = 0.1 V or VCC – 0.1 V
2.0
0.3
0.3
0.3
V
Minimum High–Level Output
Voltage
|Iout|
20
A
2.0
4.5
1.9
4.4
1.9
4.4
1.9
4.4
V
7.8 mA
5.48
5.34
5.20
V
VOL
Maximum Low–Level Output
Vin = VIH or VIL
|Iout|
6.0
2.0
6.0
0.1
0.1
0.1
0.1
0.1
0.1
6.0 mA
0.26
0.33
0.40
V
4.5
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
VCC.
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