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參數(shù)資料
| 型號： | MC74HC646 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal 3-State Bus Transceivers and D Flip-Flops |
| 中文描述： | 八路三態(tài)總線收發(fā)器和D觸發(fā)器 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 328K |
| 代理商： | MC74HC646 |
MC54/74HC646
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
(Figures 3, 4 and 9)
4.5
30
20
(Figures 1, 2 and 9)
6.0
29
24
43
tPLH,
Maximum Propagation Delay, A–to–B Clock to Output B
2.0
220
275
37
330
ns
tPHL
(or B–to–A Source to Output A)
4.5
34
51
6.0
30
43
45
tPZL,
Maximum Propagation Delay, Direction or Output Enable to
(Figures 7, 8 and 10)
2.0
6.0
175
30
220
37
265
45
ns
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 9)
2.0
4.5
60
12
37
90
18
ns
75
15
(Output in High–Impedance State)
NOTES:
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Channel)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Typical @ 25
°
C, VCC = 5.0 V
60
pF
TIMING REQUIREMENTS
(Input tr = tf = 6 ns)
Guaranteed Limit
VCC
– 55 to
(Figures 3 and 4)
6.0
17
26
th
Minimum Hold Time, A–to–B Clock to Input A
(Figures 3 and 4)
2.0
6.0
5
5
21
ns
Minimum Pulse Width, A–to–B Clock (or B–to–A Clock)
(Figures 3 and 4)
2.0
4.5
80
16
100
5
5
120
24
5
5
ns
(Figure 1)
4.5
500
500
20
500
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