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參數資料
| 型號： | MC74HC7266A |
| 廠商： | Motorola, Inc. |
| 英文描述： | SMPS Controller; Package: SOIC; No of Pins: 8; Container: Tape & Reel |
| 中文描述： | 四2輸入異或非門 |
| 文件頁數： | 4/6頁 |
| 文件大小： | 137K |
| 代理商： | MC74HC7266A |
MC74HC7266A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
LOGIC DETAIL
(1/4 of Device)
A
B
Y
APPLICATION INFORMATION
Bi
φ
–L is defined as biphase–level code. Also known as
Manchester Code, this technique utilizes binary phase shift
keying (PSK). The Bi
φ
–L output shown in Figure 3 carries
both data and synchronization information; therefore, sepa-
rate data and clock lines are not required to transfer informa-
tion. A positive–going transition in the middle of the bit
interval indicates a logic zero; a negative–going transition in-
dicates a logic one (see Figure 4).
NRZ–L shown in Figure 3 is non–return–to–zero level
code. This is simply serial data out of a shift register, such as
the HC597.
The Bi
φ
–L signal must be phase coherent (i.e., no
glitches). Therefore, NRZ–L and clock transitions must be
coincident.
Figure 3. Biphase–Level Encoder (Manchester Encoder)
NRZ–L
BI
φ
–L
CLOCK
1/4
HC7266A
POSITIVE
LOGIC DATA
1
0
1
1
0
0
BIT
INTERVAL
NRZ–L
CLOCK
BI
φ
–L
Figure 4. Timing Diagram
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