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參數資料
| 型號： | MC88PL117 |
| 廠商： | Motorola, Inc. |
| 英文描述： | CMOS PLL CLOCK DRIVER |
| 中文描述： | 的CMOS PLL時鐘驅動器 |
| 文件頁數： | 4/11頁 |
| 文件大小： | 139K |
| 代理商： | MC88PL117 |
MC88PL117
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
4
Explanation of Programmable Frequency Configurations
The MC88PL117 has six different output frequency
configurations. Figures 1 to 6 graphically depict these output
configurations. There are also three feedback frequency
options, which yields a total of 18 unique input–to–output
frequency configurations. All configurations use ‘Q’ as the
system frequency frame of reference. Therefore all output
and feedback frequencies are referenced as a multiple of Q.
Figures 1 to 6 also indicate the input levels of OPT0, OPT1,
and OPT2 for each of the eight output configurations. The
input levels of MULT0 and MULT1 are varied in these figures
to represent the different feedback (multiplication)
frequencies. The frequency of the phase shift output, Q
, is
also indicated in the figures. Tables 1. and 2. lists all 18
input/output frequency configurations. Table 3. gives the Q
phase shift increments.
OE/MR
PLL_EN
REF_SEL
OE/MR
PLL_EN
REF_SEL
OE/MR
PLL_EN
REF_SEL
OE/MR
PLL_EN
REF_SEL
Q/2 In (30MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
0
°
Phase Shift at 60MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
QFEED
LOCK
Q
MC88PL117
FIL
H
H
L
SYNC0
SYNC1
FEEDBACK
OPT2
OPT1
OPT0
L
H
H
L
H
L
MULT1
MULT0
L
H
2
1
0
Q/2 In (30MHz)
2X_Q (120MHz)
2X_Q (120MHz)
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Figure 1. Output Frequency Configuration 1
(OPT0 = L, OPT1 = L, OPT2 = L
Q/2 Input Frequency, MULT0 = H, MULT1 = L)
Figure 2. Output Frequency Configuration 2
(OPT0 = H, OPT1 = L, OPT2 = L
Q/4 Input Frequency, MULT0 = L, MULT1 = L)
Figure 3. Output Frequency Configuration 3
(OPT0 = L, OPT1 = H, OPT2 = L
Q/2 Input Frequency, MULT0 = H, MULT1 = L)
0
°
Phase Shift at 60MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
QFEED
LOCK
Q
MC88PL117
FIL
H
H
L
SYNC0
SYNC1
FEEDBACK
OPT2
OPT1
OPT0
L
H
L
L
H
L
MULT1
MULT0
L
H
2
1
0
Figure 4. Output Frequency Configuration 4
(OPT0 = H, OPT1 = H, OPT2 = L
Q/2 Input Frequency, MULT0 = H, MULT1 = L)
Q/4 In (20MHz)
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
Q/2 (30MHz)
0
°
Phase Shift at 30MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
QFEED
LOCK
Q
MC88PL117
FIL
H
H
L
SYNC0
SYNC1
FEEDBACK
OPT2
OPT1
OPT0
L
L
H
H
H
H
MULT1
MULT0
L
L
2
1
0
Q/2 In (40MHz)
2X_Q (120MHz)
2X_Q (120MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
Q (60MHz)
0
°
Phase Shift at 60MHz
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
QFEED
LOCK
Q
MC88PL117
FIL
H
H
L
SYNC0
SYNC1
FEEDBACK
OPT2
OPT1
OPT0
L
L
L
L
H
L
MULT1
MULT0
L
H
2
1
0
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