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參數資料
| 型號： | MC88PL117 |
| 廠商： | Motorola, Inc. |
| 英文描述： | CMOS PLL CLOCK DRIVER |
| 中文描述： | 的CMOS PLL時鐘驅動器 |
| 文件頁數： | 6/11頁 |
| 文件大小： | 139K |
| 代理商： | MC88PL117 |
MC88PL117
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
6
PRELIMINARY AC ELECTRICAL CHARACTERISTICS
(TA = 0 to 70
°
C, VCC = 5.0V
±
5%)
Target Specifications
Symbol
Parameter
Min
Max
Unit
Condition
50
Load
2
tskewr
Output–to–Output Skew (Same Frequency,
Coincident Rising Edges)
500
ps
tskewrall
Output–to–Output Skew (Any Frequency,
Coincident Rising Edges, Q0–Q13, QFEED)
500
ps
50
Load
2
tskewp
Part–to–Part Skew
1
1.0
ns
50
Load
2
50
Load
2
50
Load
2
tr/tf
Output Rise/Fall Time (0.8 to 2.0V)
0.15
1.0
ns
tPULSE
Output Pulse Width, All Outputs
2
(Measured at
VCC/2)
0.5tCYCLE – 0.5
0.5tCYCLE + 0.5
ns
tpd
SYNC Input to
FEEDBACK Delay
fSYNC=15MHz
fSYNC=20MHz
fSYNC=25MHz
fSYNC=30MHz
–200
–200
–100
0
400
400
500
600
ps
Feedback=Q,Q/2
fSYNC=15MHz
–50
550
Feedback=Q/4
JitterCC
Cycle–to–Cycle Jitter (Clock Period Stability)
±
250
ps
fMAX
Maximum Output Frequency for 2X_Q Outputs
8
120
MHz
50
Load
2
50
Load
2
50
Load
2
fMAX
Maximum Output Frequency for Q Outputs
4
60
MHz
fMAX
Maximum Output Frequency for Q/2 Outputs
2
30
MHz
tskew
1. This assumes that each device is running off of the same clock source with zero skew between clock source signals. A small amount of negative
offset may be present between SYNC and FEEDBACK (tPD Spec).
2. 50
load terminated to VCC/2.
Phase Accuracy of Q
versus Q or Q/2
Phase Offset – 750
Phase Offset + 250
ps
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